Abstract: Off-leak electric current is reduced in the operation mode where a circuit is actually operating. In the state in which the power supply voltage is constantly applied to the front stage flip-flops 11 to 13 and rear stage flip-flops 21 to 23, for example, data held in the flip-flops 11 to 13 at rising of the clock signal CK is processed in a logic gate circuit network 31 to which the supply voltage is applied during a low level period of the clock signal CK, and then, the processed data is held in the flip-flops 21 to 23. In the case where the power supply time to the logic gate circuit network 31 is set to minimum, off-leak electric current of the logic gate circuit network 31 can be reduced.

Abstract: A bus emulation apparatus includes serial transfer paths, serial interface circuits having a parallel to serial conversion circuit for converting parallel data from a peripheral circuit to serial data and supplying to a serial transfer path and a serial to parallel conversion circuit for converting serial data from a hub circuit to parallel data and supplying to a peripheral circuit, a hub circuit for supplying serial data from a serial interface circuit to a serial interface circuit connected to a peripheral circuit as a transfer destination of said parallel data among the serial interface circuits, and a network for connecting them, and installed on an LSI or a print circuit board to replaced a parallel bus.

Abstract: A method of frame synchronization serial data transmission. A transmitting circuit in a data communication apparatus converts frame data into serial data and transmit the same, and following the serial data, the transmitting circuit transmits frame synchronization data varying several times in the interval from an edge of a clock signal to an edge of the next clock signal; a receiving circuit receives the frame data and detects twice or more variations in the same interval to find out the end of the frame data, by receiving the serial data from a signal lines, serial data is transmitted while carrying out frame synchronization.

Abstract: A crosstalk cancellation circuit for suppressing crosstalk noise of interconnections in an integrated circuit, comprising N (N is an even number of 2 or more) number of first inverters, a first interconnection for connecting the N number of first inverters in series, N number of second inverters, and a second interconnection for connecting the N number of second inverters in series, wherein the first and second interconnections are arranged adjacent in parallel to each other, at least one first inverters is arranged at a location where crosstalk noise due to a parasitic capacity between the first and second interconnections is canceled out on the second interconnection, and at least one second inverter is arranged at a location where the crosstalk noise is canceled out on the first interconnection.

Abstract: A bus emulation apparatus includes serial transfer paths, serial interface circuits having a parallel to serial conversion circuit for converting parallel data from a peripheral circuit to serial data and supplying to a serial transfer path and a serial to parallel conversion circuit for converting serial data from a hub circuit to parallel data and supplying to a peripheral circuit, a hub circuit for supplying serial data from a serial interface circuit to a serial interface circuit connected to a peripheral circuit as a transfer destination of said parallel data among the serial interface circuits, and a network for connecting them, and installed on an LSI or a print circuit board to replaced a parallel bus.

Abstract: A delay circuit is constituted by connecting a plurality of delay elements in series, each delay element is constituted by a pMOS transistor P1 and a nMOS transistor N1 having a larger driving capability than P1 and by a nMOS transistor N2 and a pMOS transistor P2 having a larger driving capability than N2, an input signal is applied to the gate of the transistor P1, a precharge signal is applied to the gate of the transistor N1, an inverted signal of the precharge signal is applied to the gate of the transistor P2, the gate of the transistor N2 is connected to an intermediate node A, an input signal S.sub.IN is input to each delay element as the precharge signal, and when the input signal S.sub.IN is at a high level, the node A is in the state of a low level and the output terminal OUT is in the state of a high level, the falling edge of the input signal S.sub.IN is sequentially propagated by delay elements, and thus a delay signal is obtained.

Abstract: It is to realize a function clock generation circuit with which a wiring area and cell area, and further a power consumption can be reduced, and a timing design is easy. An input terminal D of a through latch circuit LTC11 is connected to an input line of an enable signal EN, an inversion clock input terminal G is connected to the input line of the clock signal, one input terminal of a NAND gate NAND11 is connected to an output terminal Q of a through latch circuit LTC11, the other input terminal is connected to the input terminal of the clock signal CK, and the output terminal is connected to the input terminal of an inverter INV11. Then, in the through latch circuit LTC11, the enable signal EN is sampled at the rising edge of the clock signal CK, and according to the value, the clock pulse immediately after the sampling is passed or blocked by the logical gate LGT comprising a NAND gate NAND11 and an inverter INV11.

Abstract: A synchronizing circuit including a plurality of latches, comprised of a first dynamic type through latch circuit and a second dynamic type through latch circuit between which is disposed a static type through latch circuit, the circuits connected in cascade. Data is sampled at the timing of the rising edge of the clock signal generated by a pulse generation circuit connected to a clock input circuit and data is output at the timing of the trailing edge. By defining the clock pulse width generated at the pulse generation circuit larger than the clock skew, it is possible to prevent malfunctions of the LSI caused by clock skew caused by deviation of timing of the clock distribution. Moreover, by providing a dynamic type through circuit for a scan test input to the first dynamic type through latch circuit in parallel, a scanning function can be realized and a malfunction due to the clock skew during scanning can be prevented.