Abstract: The purpose is to move an observation field of view of a microscope without moving or changing an objective lens without varying position or state of a sample. A microscope optical system according to the present invention has a mirror that changes the direction of the optical path by reflection and locates in the optical path between an objective lens of the microscope and an image to be observed. The mirror is able to be tilted with changing the position of a reflecting surface of the mirror. Accordingly, the observation field of view is moved by tilting the mirror. In other words, the observation field of view can be moved without changing positional relation between the objective lens of the microscope and the sample.

Abstract: A display device drive circuit that enables high-precision fine-tuning of the drive currents. In this drive circuit, a plurality of current supply transistors are connected in parallel to each data line. A switching transistor is connected in series with each current supply transistor. When the switching transistors are ON, the drive currents from the corresponding current supply transistors are supplied to the data line. The magnitude of the drive current supplied to the data line is controlled by the number of switching transistors that are ON simultaneously. Consequently, when compared to a case in which the magnitude of the drive current is controlled by the gate potential on the current supply transistors, it is possible to perform precision control of the drive current values.

Abstract: Disclosed is a liquid crystal driving semiconductor chip capable of preventing an electrostatic-surge originated malfunction. A monitor electrode for monitoring the ground potential of an external power supply circuit is provided as separate from a ground electrode 16 for power supply, the logical level of the monitor electrode is detected by an NMOS transistor in a level monitor section and a NAND gate is controlled by the detected signal. When the ground potential in the semiconductor chip drops due to, for example, a negative electrostatic surge, the logical level of the monitor electrode increases relatively to turn the NMOS transistor on, thereby setting the detected signal to “L”. As a result, the NAND gate is closed so that an enable signal from a control electrode stops being supplied to a control section, thereby preventing a malfunction originating from the erroneous enable signal.

Abstract: A microscope control apparatus is used with a microscope apparatus attached with a microscope objective lens having an aberration correction lens. The microscope control apparatus includes a memory in which information on driving amounts of the aberration correction lens that are optimum for various observation conditions respectively, entry device for allowing an observer to enter a single parameter or multiple parameters for specifying an observation condition set upon observation, and calculation device for determining a driving amount of the aberration correction lens that is optimum for the observation condition specified by the parameter(s) based on the information.

Abstract: A display device drive circuit that enables high-precision fine-tuning of the drive currents. In this drive circuit, a plurality of current supply transistors are connected in parallel to each data line. A switching transistor is connected in series with each current supply transistor. When the switching transistors are ON, the drive currents from the corresponding current supply transistors are supplied to the data line. The magnitude of the drive current supplied to the data line is controlled by the number of switching transistors that are ON simultaneously. Consequently, when compared to a case in which the magnitude of the drive current is controlled by the gate potential on the current supply transistors, it is possible to perform precision control of the drive current values.

Abstract: A memory circuit, provided with address signal generating arrangement that includes first counter 72 for outputting first output data Q1 sequentially designating address signals for memory cells under test in a memory 10, a second counter 74 for outputting second output data Q2 used to designate address signals for each memory cell of the memory 10 for every cell under test, an output control circuit 76 for selectively outputting the second output data Q2 as third output data Q3 depending on a control signal INH, and a computing circuit 78 for carrying out computations based on the first output data Q1 and the third output data Q3, and generating address signals Q4. In this way, a memory receives address signals based on a test pattern, and a tester exclusively for memory tests is not required.

Abstract: An error correction system for a difference set cyclic (272,190) code with 190 data bits and 82 test bits in a coded transmission teletext system which transmits character information on the vertical blanking interval of a television signal has been improved in peripheral circuits for operating an error correction circuit. A first improvement is to correct only designated packets which are in frame synchronization condition and/or designated by an index register. A second improvement is to handle shortened (L,k) code where L is less than 272, using common hardware. A third improvement is selection of three operational modes of data to be corrected. In the first mode, uncorrected data is supplied by an external circuit, and said uncorrected data is stored temporarily in a buffer memory, and corrected data is stored in said buffer memory again to supply external circuit corrected data. Transfer of data between the buffer memory and the error correction circuit is handled by wired logic hardware apparatus.

Abstract: An error correction system for a difference set cyclic (272, 190) code with 190 data bits and 82 test bits in a packet which is transmitted on a vertical blanking interval of a television signal has been improved. The present system comprises a buffer memory for storing an original data which is subject to correction and corrected data, and an error correction circuit having at least a syndrome register, a majority circuit and a data register. The data transfer between the buffer memory and the error correction circuit is effected by wired logic hardware means without using software operation time of a programmed computer so that computer operation time is not wasted merely for error correction.