Patents by Inventor Ichiro Shiono

Ichiro Shiono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040251458
    Abstract: A semiconductor substrate, a field effect transistor and their manufacturing methods provided with, in order to lower penetrating dislocation density and reduce surface roughness to a practical level, an Si substrate 1, a first SiGe layer 2 on the Si substrate, and a second SiGe layer 3 arranged on the first SiGe layer either directly or with an Si layer in between; wherein, the first SiGe layer has a film thickness that is thinner than twice the critical film thickness, which is the film thickness at which dislocation occurs resulting in lattice relaxation due to increased film thickness, the Ge composition ratio of the second SiGe layer is at least lower than the intralayer maximum value of the Ge composition ratio in the first SiGe layer or in the first SiGe layer at the contact surface with the Si layer, and the second SiGe layer has an incremental composition region in which the Ge composition ratio gradually increases towards the surface at least in a portion thereof.
    Type: Application
    Filed: February 4, 2004
    Publication date: December 16, 2004
    Inventors: Kazuki Mizushima, Ichiro Shiono, Kenji Yamaguchi
  • Publication number: 20040245552
    Abstract: The present invention relates to a semiconductor substrate production method, field effect transistor production method, semiconductor substrate and field effect transistor which, together with having low penetrating dislocation density and low surface roughness, prevent worsening of surface and interface roughness during heat treatment of a device production process and so forth. A production method of a semiconductor substrate W, in which SiGe layers 2 and 3 are formed on an Si substrate 1, is comprised of a heat treatment step in which heat treatment is performed either during or after the formation of the SiGe layers by epitaxial growth, at a temperature that exceeds the temperature of the epitaxial growth, and a polishing step in which irregularities in the surface formed during the heat treatment are removed by polishing following formation of the SiGe layers.
    Type: Application
    Filed: February 20, 2004
    Publication date: December 9, 2004
    Inventors: Ichiro Shiono, Kazuki Mizushima, Kenji Yamaguchi
  • Patent number: 6525338
    Abstract: A semiconductor substrate, a field effect transistor, a method of forming a SiGe layer and a method of forming a strained Si layer using the same, and a method of manufacturing a field effect transistor are provided, which enable the threading dislocation density of the SiGe layer to be reduced and the surface roughness to be minimized. On top of a Si substrate 1 is provided a SiGe buffer layer 2, 12 constructed of a plurality of laminated layers comprising alternating layers of a SiGe gradient composition layer 2a, 12a in which the Ge composition ratio increases gradually from the Ge composition ratio of the base material, and a SiGe constant composition layer 2b, 12b which is provided on top of the gradient composition layer and in which the Ge composition ratio is equal to that of the upper surface of the gradient composition layer.
    Type: Grant
    Filed: July 31, 2001
    Date of Patent: February 25, 2003
    Assignees: Mitsubishi Materials Corporation, Mitsubishi Materials Silicon Corporation
    Inventors: Kazuki Mizushima, Ichiro Shiono, Kenji Yamaguchi
  • Publication number: 20020017642
    Abstract: A semiconductor substrate, a field effect transistor, a method of forming a SiGe layer and a method of forming a strained Si layer using the same, and a method of manufacturing a field effect transistor are provided, which enable the threading dislocation density of the SiGe layer to be reduced and the surface roughness to be minimized. On top of a Si substrate 1 is provided a SiGe buffer layer 2, 12 constructed of a plurality of laminated layers comprising alternating layers of a SiGe gradient composition layer 2a, 12a in which the Ge composition ratio increases gradually from the Ge composition ratio of the base material, and a SiGe constant composition layer 2b, 12b which is provided on top of the gradient composition layer and in which the Ge composition ratio is equal to that of the upper surface of the gradient composition layer.
    Type: Application
    Filed: July 31, 2001
    Publication date: February 14, 2002
    Applicant: MITSUBISHI MATERIALS CORPORATION
    Inventors: Kazuki Mizushima, Ichiro Shiono, Kenji Yamaguchi