Abstract: A CMOS logical circuit comprises two electric current paths each of which has circuits consisting of n-type and p-type transistors. In a circuit consisting of n-type or p-type transistors, one electric current path is provided with a circuit having the same construction as that of a circuit having an n-type transistor of a CMOS logical circuit outputting a logical operation result similar to that of this logical circuit, and the other electric current path is provided with a circuit having the same construction as that of a circuit having a p-type transistor of the CMOS logical circuit outputting a logical operation result similar to that of this logical circuit. In another circuit consisting of the other channel type, a gate electrode of the transistor provided on the one electric current path and that of the transistor provided on the other electric current path are connected to drain electrodes of the counterparts.

Abstract: A display device includes: a plurality of signal lines which extend in a zigzag manner in a column direction and to which image signals are supplied, respectively; an insulation film which covers the plurality of signal lines; and a plurality of pixel electrodes which are formed on the insulation film and to which the image signals are input from the plurality of signal lines, respectively. A distance between ones of the pixel electrodes located adjacent to each other in the column direction is equal to or larger than a line width of the signal lines.

Abstract: A first electrode substrate of the present invention includes a first signal line, a second signal line, a third signal line, a first pixel electrode, a second pixel electrode, and a third pixel electrode. The first signal line, the second signal line and the third signal line extend in a first direction and in parallel to one another. The first pixel electrode is electrically connected to the first signal line. The second pixel electrode is adjacent to the first pixel electrode in the first direction, and is electrically connected to the second signal line. The third pixel electrode is adjacent to the second pixel electrode in the row direction, crossing the first direction, via the second signal line therebetween, and is electrically connected to the third signal line.

Abstract: A display device includes a source line for supplying a display signal, a display pixel electrode, and a TFT for switching an electrical connection between the source line and the pixel electrode. The TFT includes a source electrode electrically connected to the source line, a drain electrode electrically connected to the pixel electrode, and a gate electrode for controlling an electrical connection between the source electrode and the drain electrode. A first auxiliary capacitor electrode and a second auxiliary capacitor electrode are connected to the drain electrode and respective connection portions between the drain electrode and the auxiliary capacitor electrodes are formed of a semiconductor material.

Abstract: In a multi-gap semi-transmissive liquid crystal display device, the width of a black matrix (6) is made larger above the region between adjacent ITO transparent electrodes (3) and is made smaller above the region between adjacent Al reflective electrodes (4). This enables a transmissive portion to offer a display with high contrast that does not suffer from afterimage or the like by shielding light from the domain lying between the adjacent pixels, and the reflective portion to offer a brighter display by increasing the aperture ratio thereof by making the black matrix width as small as possible or forming no black matrix.

Abstract: A display device of the present invention comprises: a source line; a pixel electrode; a first TFT for switching an electrical connection between the source line and the pixel electrode; and a second TFT as a spare. The second TFT includes a semiconductor film and a gate electrode. The semiconductor film includes a source electrode and a drain electrode. The gate electrode is provided on the semiconductor film with a gate insulation film interposed therebetween. The display device includes an interlayer insulation film between the source line and the semiconductor film of the second TFT. The interlayer insulation film is thicker than the gate insulation film. When the first TFT is unusable, a contact hole is formed in the interlayer insulation film such that the source line is electrically connected to the source electrode, whereby the electrical connection between the source line and the pixel electrode is rendered switchable by the second TFT.

Abstract: A CMOS logical circuit comprises two electric current paths each of which has circuits consisting of n-type and p-type transistors. In a circuit consisting of n-type or p-type transistors, one electric current path is provided with a circuit having the same construction as that of a circuit having an n-type transistor of a CMOS logical circuit outputting a logical operation result similar to that of this logical circuit, and the other electric current path is provided with a circuit having the same construction as that of a circuit having a p-type transistor of the CMOS logical circuit outputting a logical operation result similar to that of this logical circuit. In another circuit consisting of the other channel type, a gate electrode of the transistor provided on the one electric current path and that of the transistor provided on the other electric current path are connected to drain electrodes of the counterparts.

Abstract: A display device of the present invention comprises: a source line; a pixel electrode; a first TFT for switching an electrical connection between the source line and the pixel electrode; and a second TFT as a spare. The second TFT includes a semiconductor film and a gate electrode. The semiconductor film includes a source electrode and a drain electrode. The gate electrode is provided on the semiconductor film with a gate insulation film interposed therebetween. The display device includes an interlayer insulation film between the source line and the semiconductor film of the second TFT. The interlayer insulation film is thicker than the gate insulation film. When the first TFT is unusable, a contact hole is formed in the interlayer insulation film such that the source line is electrically connected to the source electrode, whereby the electrical connection between the source line and the pixel electrode is rendered switchable by the second TFT.

Abstract: A display device includes a source line for supplying a display signal, a display pixel electrode, and a TFT for switching an electrical connection between the source line and the pixel electrode. The TFT includes a source electrode electrically connected to the source line, a drain electrode electrically connected to the pixel electrode, and a gate electrode for controlling an electrical connection between the source electrode and the drain electrode. A first auxiliary capacitor electrode and a second auxiliary capacitor electrode are connected to the drain electrode and respective connection portions between the drain electrode and the auxiliary capacitor electrodes are formed of a semiconductor material.

Abstract: A display device includes: a plurality of signal lines which extend in a zigzag manner in a column direction and to which image signals are supplied, respectively; an insulation film which covers the plurality of signal lines; and a plurality of pixel electrodes which are formed on the insulation film and to which the image signals are input from the plurality of signal lines, respectively. A distance between ones of the pixel electrodes located adjacent to each other in the column direction is equal to or larger than a line width of the signal lines.

Abstract: A shield electrode is provided in the vicinity of a pixel electrode and source bus lines. The shield electrode may be provided in the same layer as gate bus lines, or in the same layer as the source bus lines. The shield electrode may be surrounded by an insulating material, or may be connected to a line other than the source bus lines. By providing the shield electrode, it is possible to reduce a source-drain parasitic capacitance between a pixel electrode and a source bus line.

Abstract: A CMOS logical circuit comprises two electric current paths each of which has circuits consisting of n-type and p-type transistors. In a circuit consisting of n-type or p-type transistors, one electric current path is provided with a circuit having the same construction as that of a circuit having an n-type transistor of a CMOS logical circuit outputting a logical operation result similar to that of this logical circuit, and the other electric current path is provided with a circuit having the same construction as that of a circuit having a p-type transistor of the CMOS logical circuit outputting a logical operation result similar to that of this logical circuit. In another circuit consisting of the other channel type, a gate electrode of the transistor provided on the one electric current path and that of the transistor provided on the other electric current path are connected to drain electrodes of the counterparts.

Abstract: If a clock signal ck is “H” and an input pulse signal in (first control signal) is “H”, then n-type transistors M15 and M16 are turned on to make an output node/OUT have the GND level. Then, a p-type transistor M12 is turned on to make an output node OUT have a Vcc (16 V) level. Thus, a latch circuit LAT operates as a level shifter circuit when first and second control signals and the clock signal ck are at “H” and operates as a level hold circuit in any other case. Therefore, the shift register circuit constructed of the latch circuit LAT functions as a low-voltage interface, and the input of the clock signal ck is stopped when the latch circuit LAT is inactive, so that the load and the consumption of power of the clock signal line are reduced.

Abstract: An active-matrix-type image display device having a gray-scale power supply for generating gray-scale voltages of different levels, and a source driver that applies gray-scale voltages according to a digital picture signal to source lines and includes one scanning circuit for each source line. The outputs of the scanning circuits are sequentially made active once in a horizontal period. A latch circuit fetches the digital picture signal in synchronization with making the output of the scanning circuit active. The digital picture signal is decoded by a decoder circuit, and one of analog switches becomes a conducting state according to the decoded signal. As a result, one of the gray-scale voltages is output to the source line.

Abstract: A semiconductor device includes a first conductive layer; an interlayer insulative layer having an opening; and a second conductive layer. The first conductive layer, the interlayer insulative layer and the second conductive layer are sequentially laminated. The opening is partially covered by the second conductive layer, and an area of the first conductive layer is substantially entirely covered by the second conductive layer in the opening.

Abstract: A shift register circuit, composed of a plurality of serially connected latch circuits, for sequentially transmitting a pulse signal in sync with a rising and a falling of a clock signal, and an output circuit for sequentially outputting a video signal to data signal lines in sync with the pulse signal outputted from the shift register circuit are provided. The shift register circuit is divided into a plurality of latch circuit groups, and the stage numbers of the latch circuits in each latch circuit group is set in such a manner to minimize the time difference between the pulse signal outputted from each latch circuit group and the video signal outputted in sync with the pulse signal.

Abstract: A matrix-type image display device of the present invention is arranged such that image data are selectively applied to pixels arranged in a matrix form through scanning signal lines and data signal lines, and the image data are stored therein, wherein a high potential of a sampling pulse 0V/5V to be output from a logic circuit is shifted to 10 V, and a low potential thereof is shifted to −8 V respectively by first and second level shifters. As a result, a difference between an input signal level from an external circuit such as a control circuit, an image signal processing circuit, etc., and an actual driving signal level of each pixel can be absorbed. Therefore, an additional structure such as an interface circuit, etc., is not needed between the external circuit and the scanning signal line driving circuit, thereby enabling a low cost and a low power consumption.

Abstract: An active matrix type liquid crystal display device carries out half-tone display with an area gray scale display method, according to which a pixel is composed of a plurality of subpixels and the area of display regions is changed by an image signal that is a binary signal. The amplitude of an opposite electrode is optimized by configuring a data signal line driving circuit with a scanning circuit, latch-in circuits and outputting circuits. This eliminates the needs to externally input an analogue signal and an intermediate voltage, and enables the driving circuit to be configured only with digital circuits. The driving circuit is integrated to prevent increases in cost of the driving circuit and of mounting the driving circuit that are caused by an increase in the number of data signal lines as a result of the adoption of the area gray scale display method. Consequently, it becomes possible to make an attempt to reduce the cost, power consumption and non-defective ratio of the entire system.

Abstract: A delay detecting section detects the phase difference between a first detection signal as a reference and a second detection signal produced by delaying the first detection signal with part of a data signal line driving circuit itself or part of a circuit formed by the same process as the data signal line driving circuit. A phase adjusting section presumes an internal delay of the data signal line driving circuit, and adjusts the phase difference between a clock signal and start signal, and a video signal so that the data signal line driving circuit samples the video signal at an appropriate timing. These structures prevent a lowering of the image quality due to a difference in the timings of the video signal and sampling signal, and provide an image display device capable of displaying a good-quality image with a simple circuit structure.

Abstract: A semiconductor device includes a first conductive layer; an interlayer insulative layer having an opening; and a second conductive layer. The first conductive layer, the interlayer insulative layer and the second conductive layer are sequentially laminated. The opening is partially covered by the second conductive layer, and an area of the first conductive layer is substantially entirely covered by the second conductive layer in the opening.