Patents by Inventor Ichiro Shiraki

Ichiro Shiraki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20010011983
    Abstract: An active-matrix-type image display device having a gray-scale power supply for generating gray-scale voltages of different levels, and a source driver that applies gray-scale voltages according to a digital picture signal to source lines and includes one scanning circuit for each source line. The outputs of the scanning circuits are sequentially made active once in a horizontal period. A latch circuit fetches the digital picture signal in synchronization with making the output of the scanning circuit active. The digital picture signal is decoded by a decoder circuit, and one of analog switches becomes a conducting state according to the decoded signal. As a result, one of the gray-scale voltages is output to the source line.
    Type: Application
    Filed: June 2, 1998
    Publication date: August 9, 2001
    Inventors: ICHIRO SHIRAKI, YASUSHI KUBOTA, TAMOTSU SAKAI
  • Patent number: 6225866
    Abstract: A sampling circuit is arranged so that source voltages VDD and VEE, which are to be applied to two inverters at the latter stages in a signal path on the p-channel transistor side, are shifted to the positive side with respect to source voltages VCC and VSS that are applied to the other inverters. With such a power supply construction, video signals on the low-potential side in a video signal line are picked up by the n-channel transistor and video signals on the high-potential side are picked up by the p-channel transistor, and the resulting signals are supplied to a data signal line. This arrangement makes it possible to reduce the gate input voltage upon conduction of the sampling switch. Moreover, by shifting the levels of the source voltages as described above, it becomes possible to ensure writing and holding operations even in the case of having signals with a small amplitude.
    Type: Grant
    Filed: June 14, 2000
    Date of Patent: May 1, 2001
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasushi Kubota, Ichiro Shiraki
  • Patent number: 6157361
    Abstract: A matrix-type image display device of the present invention is arranged such that image data are selectively applied to pixels arranged in a matrix form through scanning signal lines and data signal lines, and the image data are stored therein, wherein a high potential of a sampling pulse 0V/5V to be output from a logic circuit is shifted to 10 V, and a low potential thereof is shifted to -8 V respectively by first and second level shifters. As a result, a difference between an input signal level from an external circuit such as a control circuit, an image signal processing circuit, etc., and an actual driving signal level of each pixel can be absorbed. Therefore, an additional structure such as an interface circuit, etc., is not needed between the external circuit and the scanning signal line driving circuit, thereby enabling a low cost and a low power consumption.
    Type: Grant
    Filed: July 14, 1997
    Date of Patent: December 5, 2000
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasushi Kubota, Ichiro Shiraki, Tamotsu Sakai
  • Patent number: 5977944
    Abstract: A data signal output circuit is divided into a plurality of blocks, each having its own supply circuit. In each block, a plurality of shift register sections, constituting a shift register, output pulse signals which have been shifted according to clock signals. Driving sections sample a digital image signal in synchronism with the pulse signal, and output data signals corresponding to the image signal thus sampled to a plurality of output lines. Each supply circuit provided in the blocks receives the image signal when the image signal should be sampled by the driving sections, thereby supplying the image signal only to the minimum number of blocks to be operated. In this manner, the image signal is selectively supplied to the block so as to reduce the effective load on the image signal. As a result, the power consumption generated in the image signal lines can be reduced.
    Type: Grant
    Filed: August 11, 1997
    Date of Patent: November 2, 1999
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasushi Kubota, Kenichi Katoh, Ichiro Shiraki
  • Patent number: 5952854
    Abstract: A sampling circuit for sampling an analog signal in accordance with a timing signal includes a sampling switching element having a CMOS configuration. The sampling switching element includes an n-channel transistor and a p-channel transistor connected in parallel. The drive power and the feedthrough voltage are substantially the same in the n-channel transistor and the p-channel transistor. The sampling circuit, for example, is continued with an image display device.
    Type: Grant
    Filed: September 5, 1996
    Date of Patent: September 14, 1999
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasushi Kubota, Ichiro Shiraki, Tamotsu Sakai
  • Patent number: 5926234
    Abstract: Picture elements and driving circuits for driving respective picture elements are monolithically formed on an insulating substrate. A protective circuit is provided for allowing input-output terminals of a driving circuit to conduct when a potential difference of not less than a predetermined value is generated. The protective circuit includes an MOS transistor, and a turn-on voltage thereof is set according to a thickness of a gate insulating layer. The protective circuit is formed on the insulating substrate simultaneously when forming the driving circuits. In this arrangement, because the turn-on voltage is set according to the thickness of the gate insulating layer and the thickness can be easily adjusted, an accurate turn-on voltage can be achieved. Since the arrangement prevents an increase in manufacturing cost, the driving circuits, etc., can be surely protected against static electricity generated in the manufacturing process and the input surge in the normal operation.
    Type: Grant
    Filed: June 17, 1997
    Date of Patent: July 20, 1999
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Ichiro Shiraki, Yasushi Kubota, Hiroshi Yoneda
  • Patent number: 5926156
    Abstract: A driving circuit in a matrix type image display apparatus including a plurality of groups each including four standard unit circuits and one backup unit circuit. Each standard unit circuit includes disconnecting means for isolating the standard unit circuit from the driving circuit, and the backup unit circuit includes connecting means for connecting the backup unit circuit to an input signal line and an output signal line of any of the standard unit circuits within a group. The number of the backup unit circuits can be changed in accordance with a conforming ratio of each unit circuit, which makes it possible to eliminate idle backup unit circuits while maintaining a high overall conforming ratio of the driving circuit, thereby enhancing manufacturing efficiencies and reducing manufacturing costs.
    Type: Grant
    Filed: November 9, 1995
    Date of Patent: July 20, 1999
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kenichi Katoh, Yasushi Kubota, Hiroshi Yoneda, Osamu Sasaki, Ichiro Shiraki
  • Patent number: 5844538
    Abstract: An image display apparatus can be arranged so that a picture element capacity obtains a value provides display data retention of less than 99% by writing same data to a picture element a plurality of times during 1 frame period. This makes it possible to disuse the auxiliary capacity and to improve an aperture ratio. Moreover, with the present invention, an MOS transistor arranged in each picture element as a switching element for driving the picture element, a scan signal line driving circuit and a data signal line driving circuit for transmitting a driving signal based upon display data to the MOS transistor through a data signal line and a scan signal line, and a first frame memory and a second frame memory provided outside the picture element for storing display data to be outputted to a data signal line driving circuit for 1 frame are formed on one substrate. As a result, it is possible to improve package efficiency and lower cost by using a driver monolithic technique.
    Type: Grant
    Filed: December 23, 1994
    Date of Patent: December 1, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Ichiro Shiraki, Manabu Matsuura, Yasushi Kubota, Hiroshi Yoneda, Yoshitaka Yamamoto
  • Patent number: 5790213
    Abstract: A liquid crystal display device includes pixels, arranged in a two-dimensional matrix on a substrate, for displaying an image, and several types of transistors, fabricated monolithically on the substrate for driving the respective pixels. One transistor in each pixel is juxtaposed on a periphery section of an adjacent pixel. By sharing such sections between adjacent pixels the fabrication of the transistors is simplified with the area occupied by each transistor and the pixel size reduced.
    Type: Grant
    Filed: September 5, 1995
    Date of Patent: August 4, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Osamu Sasaki, Ichiro Shiraki, Manabu Matsuura, Hiroshi Yoneda
  • Patent number: 5754155
    Abstract: In an image display device, a reference voltage generating circuit of a power supply circuit, which applies power supply voltages V.sub.GH and V.sub.GL to a scan signal line driving circuit, is formed on a substrate where picture elements for display are formed, and a transistor which composes the reference voltage generating circuit has the approximately same threshold voltage as a picture element transistor TR.sub.(PIX) which composes the picture elements for display. As a result, the power supply voltages V.sub.GH and V.sub.GL to the scan signal line driving circuit automatically obtain which is optimized for a characteristic of the transistor TR(PIX) which composes the picture elements for display. Therefore, the power supply voltages V.sub.GH and V.sub.GL do not require adjustment per picture element array or every time when the usage environment is changed. As a result, the cost of adjustment is reduced and convenience of the usage is improved.
    Type: Grant
    Filed: January 25, 1996
    Date of Patent: May 19, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasushi Kubota, Ichiro Shiraki
  • Patent number: 5671026
    Abstract: Picture elements and driving circuits for driving respective picture elements are monolithically formed on an insulating substrate. A protective circuit is provided for allowing input-output terminals of a driving circuit to conduct when a potential difference of not less than a predetermined value is generated. The protective circuit includes an MOS transistor, and a turn-on voltage thereof is set according to a thickness of a gate insulating layer. The protective circuit is formed on the insulating substrate simultaneously when forming the driving circuits. In this arrangement, because the turn-on voltage is set according to the thickness of the gate insulating layer and the thickness can be easily adjusted, an accurate turn-on voltage can be achieved. Since the arrangement prevents an increase in manufacturing cost, the driving circuits, etc., can be surely protected against static electricity generated in the manufacturing process and the input surge in the normal operation.
    Type: Grant
    Filed: February 27, 1995
    Date of Patent: September 23, 1997
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Ichiro Shiraki, Yasushi Kubota, Hiroshi Yoneda