Patents by Inventor Ichiro Yamane

Ichiro Yamane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5767009
    Abstract: The present invention reduces crosstalk noise, which occurs as a result of interference between signals running in each of respective wiring layers of a first semiconductor chip and a second semiconductor chip stacked surface to surface with a small gap. The semiconductor device includes a first semiconductor chip (1) having a first electrode pad (2) and a first wiring layer (9), and a second semiconductor chip (5) having a second electrode pad (6) and a second wiring layer (10). A bump (4) is provided for electrically coupling the first electrode pad (2) and the second electrode pad (6). An insulation layer 8 is disposed between confronting surfaces of the first semiconductor chip (1) and the second semiconductor chip (5). An electro-conductive layer (7) is disposed between the confronting surfaces of the first semiconductor chip and the second semiconductor chip.
    Type: Grant
    Filed: February 10, 1997
    Date of Patent: June 16, 1998
    Assignees: Matsushita Electric Industrial Co., Ltd., Matsushita Electronics Corp.
    Inventors: Takayuki Yoshida, Takashi Otsuka, Hiroaki Fujimoto, Tadaaki Mimura, Ichiro Yamane, Takio Yamashita, Toshio Matsuki, Yoshiaki Kasuga
  • Patent number: 5734199
    Abstract: The main surface of a first semiconductor chip having a first functional element is formed with first testing electrodes for testing the electrical characteristics of the first functional element and first connecting electrodes electrically connected to the first functional element. The main surface of a second semiconductor chip having a second functional element is formed with second testing electrodes for testing the electrical characteristics of the second functional element and second connecting electrodes electrically connected to the second functional element. The first semiconductor chip and the second semiconductor chip are integrated by using an insulating resin, with first bumps formed on the first connecting electrodes being bonded to third bumps formed on the second connecting electrodes.
    Type: Grant
    Filed: December 17, 1996
    Date of Patent: March 31, 1998
    Assignees: Matsushita Electric Industrial Co., Ltd., Matsushita Electronics Corporation
    Inventors: Tetsuo Kawakita, Kazuhiko Matsumura, Ichiro Yamane
  • Patent number: 4334020
    Abstract: A mutant of the genus Brevibacterium or Corynebacterium resistant to a compound having vitamine-P activity produces L-glutamic acid in a high yield, when it is cultured in an aqueous medium aerobically.
    Type: Grant
    Filed: June 6, 1980
    Date of Patent: June 8, 1982
    Assignee: Ajinomoto Company Incorporated
    Inventors: Hidetsugu Nakazawa, Ichiro Yamane, Eiichi Akutsu