Abstract: An integrated circuit (IC) includes one or more testable voltage decoupling (DCAP) cells. Each of the testable DCAP cells includes (i) one or more decoupling capacitors connected between supply rails of the IC, and (ii) a decoupling-test active logic (DTAL) circuit, which has a normal input-output response and is configured to deviate from the normal input-output response in response to a fault in the DCAP cell.

Abstract: An electronic device includes a first integrated circuit (IC) die and a second IC die. The first IC die includes a first set of contact pads arranged in a first geometrical pattern on a first surface of the first IC die, the second IC die includes a second set of the contact pads that are arranged, on a second surface of the second IC die, in a second geometrical pattern that is a mirror image of the first geometrical pattern. The second surface of the second IC die is facing the first surface of the first IC die, and the contact pads of the first and second sets are aligned with one another and mounted on one another.

Abstract: An electronic device includes a substrate having contact pads disposed thereon and traces interconnecting the contact pads. A first integrated circuit (IC) die is mounted on the substrate and includes a predefined set of circuit components arranged on the first IC die in a first geometrical pattern, which is non-symmetrical under reflection about a given axis in a plane of the die. A second IC die is mounted on the substrate and includes the predefined set of circuit components arranged on the second IC die in a second geometrical pattern, which is a mirror image of the first geometrical pattern with respect to the given axis.

Abstract: An electronic device includes a substrate having contact pads disposed thereon and traces interconnecting the contact pads. A first integrated circuit (IC) die is mounted on the substrate and includes a predefined set of circuit components arranged on the first IC die in a first geometrical pattern, which is non-symmetrical under reflection about a given axis in a plane of the die. A second IC die is mounted on the substrate and includes the predefined set of circuit components arranged on the second IC die in a second geometrical pattern, which is a mirror image of the first geometrical pattern with respect to the given axis.

Abstract: An apparatus for testing an Integrated Circuit (IC) to be installed on a product substrate of a Multi-Chip Module (MCM) is disclosed. The apparatus includes a test substrate including (i) a first surface configured to receive the tested IC and at least an additional IC, (ii) a second surface that is opposite the first surface and is configured to receive electrical contacts, and (iii) first electrical traces for conveying electrical signals between the tested IC, the additional IC and the electrical contacts. The apparatus further includes a second electrical trace, which is formed in the test substrate instead of the additional IC and is configured to electrically connect between two of the first electrical traces.

Abstract: A method includes obtaining (i) an operating-temperature profile of a hardware processing sub-unit (HPSU) of a network element as a function of time, and (ii) a dependence of an Equivalent Reliability Time (ERT) of the HPSU on operating temperature. The operating-temperature profile is weighted using the dependence of the ERT on operating temperature, to estimate an effective ERT of the HPSU. An operating condition of the HPSU in the network element is modified, depending on the effective ERT.

Abstract: A method includes obtaining (i) an operating-temperature profile of a hardware processing sub-unit (HPSU) of a network element as a function of time, and (ii) a dependence of an Equivalent Reliability Time (ERT) of the HPSU on operating temperature. The operating-temperature profile is weighted using the dependence of the ERT on operating temperature, to estimate an effective ERT of the HPSU. An operating condition of the HPSU in the network element is modified, depending on the effective ERT.

Abstract: An apparatus for testing an Integrated Circuit (IC) to be installed on a product substrate of a Multi-Chip Module (MCM) is disclosed. The apparatus includes a test substrate including (i) a first surface configured to receive the tested IC and at least an additional IC, (ii) a second surface that is opposite the first surface and is configured to receive electrical contacts, and (iii) first electrical traces for conveying electrical signals between the tested IC, the additional IC and the electrical contacts. The apparatus further includes a second electrical trace, which is formed in the test substrate instead of the additional IC and is configured to electrically connect between two of the first electrical traces.

Abstract: A method for circuit design includes providing one or more wrapper cells for use with a library of standard cells in design of an IC. Each wrapper cell has geometrical dimensions matching a corresponding group of one or more of the standard cells and defines an electrical path, including at least one via, from a location of a terminal in a lower metal layer in the standard cells in the corresponding group to a location in an upper metal layer. A computerized place-and-route tool receives a layout of the IC including a wrapper cell superimposed over one of the standard cells in the corresponding group. The place-and-route tool automatically routes a signal connection through the upper metal layer and the at least one via defined by the superimposed wrapper cell to the predefined signal terminal in the lower metal layer in the one of the standard cells.

Abstract: A method for circuit design includes providing one or more wrapper cells for use with a library of standard cells in design of an IC. Each wrapper cell has geometrical dimensions matching a corresponding group of one or more of the standard cells and defines an electrical path, including at least one via, from a location of a terminal in a lower metal layer in the standard cells in the corresponding group to a location in an upper metal layer. A computerized place-and-route tool receives a layout of the IC including a wrapper cell superimposed over one of the standard cells in the corresponding group. The place-and-route tool automatically routes a signal connection through the upper metal layer and the at least one via defined by the superimposed wrapper cell to the predefined signal terminal in the lower metal layer in the one of the standard cells.

Abstract: An optoelectronic device includes an optoelectronic die, a laser die, and electrical interconnects. The optoelectronic device has a surface. A trench having first and second walls and a floor is formed in the surface, and an electrically conductive layer extends from the floor, via the first wall, to the surface. The laser die includes first and second electrodes and a laser output aperture. The laser die is mounted in the trench and is configured to emit a laser beam. The first electrode is coupled to the electrically conductive layer and the laser output aperture is mechanically aligned with a waveguide that extends from the second wall. The interconnects are formed on the second electrode of the laser die and on selected locations on the surface of the optoelectronic die. The interconnects are coupled to a substrate, and are configured to conduct electrical signals between the optoelectronic die and the substrate.

Abstract: An optoelectronic device includes an optoelectronic die, a laser die, and electrical interconnects. The optoelectronic device has a surface. A trench having first and second walls and a floor is formed in the surface, and an electrically conductive layer extends from the floor, via the first wall, to the surface. The laser die includes first and second electrodes and a laser output aperture. The laser die is mounted in the trench and is configured to emit a laser beam. The first electrode is coupled to the electrically conductive layer and the laser output aperture is mechanically aligned with a waveguide that extends from the second wall. The interconnects are formed on the second electrode of the laser die and on selected locations on the surface of the optoelectronic die. The interconnects are coupled to a substrate, and are configured to conduct electrical signals between the optoelectronic die and the substrate.

Abstract: Aspects of the disclosure provide a circuit including an encoding circuit and a valid circuit. The encoding circuit is configured to encode data to be transmitted as signals on a data bus to satisfy a requirement that limits a number of bit transitions between consecutive transmissions. The valid circuit is configured to selectively corrupt the signals not to satisfy the requirement that limits the number of bit transitions between the consecutive transmissions to indicate whether the signals to be transmitted on the data bus constitute valid data or invalid data.

Abstract: Some of the embodiments of the present disclosure provide an apparatus for sensing a voltage level of an output voltage that is selected from at least two voltage supplies, including: a maximum voltage generator circuit configured (i) to determine a voltage supply among the at least two voltage supplies that has a higher voltage level and (ii) to output a maximum voltage signal having a voltage level corresponding to the higher voltage level; and a sensing module configured to selectively sense the output voltages, the sensing module comprising a switch circuit configured to apply the maximum voltage signal to completely turn off supply of the output voltage when the output voltage is not to be sensed at the sensing module.

Abstract: Aspects of the disclosure provide an integrated circuit (IC). The IC includes an input interface and a controller. The input interface is configured to receive an input signal providing information for controlling a supply voltage based on a performance characteristic of another IC. The controller is configured to generate an output signal for controlling the supply voltage based on a combination of the input signal and a performance characteristic of the IC.

Abstract: Systems and methods are provided for an interposer for coupling two or more integrated circuit dies to a circuit package. A first integrated circuit portion is disposed on a first location of a single semiconductor substrate. A second integrated circuit portion is disposed on a second location of the single semiconductor substrate, where the second integrated circuit portion is electrically isolated from the first integrated circuit portion along a first axis. The first and second integrated circuit portions are configured to provide an electrical coupling to two or more corresponding top die integrated circuits across a second axis that is perpendicular to the first axis.

Abstract: Aspects of the disclosure provide an integrated circuit (IC) chip that includes a feedback control circuit and a detecting circuit. The feedback control circuit is configured to govern a feedback signal to a first regulator that regulates a first power supply to the IC chip based on the feedback signal. The feedback control circuit is powered at least partially by a second power supply. The detecting circuit is configured to detect a power down of the second power supply, and to cause the feedback control circuit to be disengaged from the feedback signal in response to the power down.

Abstract: Some of the embodiments of the present disclosure provide a system comprising a functional block; a plurality of power sources, each of the plurality of power sources being maintained at a corresponding voltage; and a switching module having a plurality of switches, the switching module configured to supply power from at least one of the plurality of power sources to the functional block, each of the plurality of switches being controlled by a corresponding switching signal having a voltage value that is one of (i) a ground voltage and (ii) a high max voltage, the high max voltage corresponding to a highest voltage among the voltages of the plurality of power sources. Other embodiments are also described and claimed.

Abstract: Aspects of the disclosure provide a method. The method includes causing a voltage level of a signal transmitted on a transmission line to be non-linearly modified to reduce a voltage variation at a target level, and providing the modified signal to a receiving circuit that is disposed on the transmission line. In an embodiment, the method includes causing the voltage level of the signal transmitted on the transmission line to be non-linearly modified to reduce a first voltage variation at a first target level corresponding to a first digital value and to reduce a second voltage variation at a second target level corresponding to a second digital value.

Abstract: Aspects of the disclosure provide a circuit including an encoding circuit and a valid circuit. The encoding circuit is configured to encode data to be transmitted as signals on a data bus to satisfy a requirement that limits a number of bit transitions between consecutive transmissions. The valid circuit is configured to selectively corrupt the signals not to satisfy the requirement that limits the number of bit transitions between the consecutive transmissions to indicate whether the signals to be transmitted on the data bus constitute valid data or invalid data.