Abstract: Systems and methods are provided for an interposer for coupling two or more integrated circuit dies to a circuit package. A first integrated circuit portion is disposed on a first location of a single semiconductor substrate. A second integrated circuit portion is disposed on a second location of the single semiconductor substrate, where the second integrated circuit portion is electrically isolated from the first integrated circuit portion along a first axis. The first and second integrated circuit portions are configured to provide an electrical coupling to two or more corresponding top die integrated circuits across a second axis that is perpendicular to the first axis.

Abstract: Aspects of the disclosure provide an integrated circuit (IC). The IC includes a clock generation and supply voltage monitoring circuit configured to monitor a supply voltage to the IC and selectively modify an operating frequency of the IC in response to a sensed change in the supply voltage. The IC further includes a frequency comparing and compensating circuit configured to output a control signal, based on the operating frequency, to a voltage supply to modify the supply voltage so as to compensate for changes in the operating frequency and return the operating frequency to a target operating frequency.

Abstract: Systems and methods are provided for an interposer for coupling two or more integrated circuit dies to a circuit package. A first integrated circuit portion is disposed on a first location of a single semiconductor substrate. A second integrated circuit portion is disposed on a second location of the single semiconductor substrate, where the second integrated circuit portion is electrically isolated from the first integrated circuit portion along a first axis. The first and second integrated circuit portions are configured to provide an electrical coupling to two or more corresponding top die integrated circuits across a second axis that is perpendicular to the first axis.

Abstract: An integrated circuit includes an operational circuit module receiving a supply voltage from a voltage regulator external to the integrated circuit, and an adaptive voltage scaling module to adjust the supply voltage based on performance characteristics of the operational circuit module. The adaptive voltage scaling module can include a performance monitoring module disposed on the integrated circuit and configured to generate at least an indicator corresponding to at least one performance characteristic of the operational circuit module. The adaptive scaling module can include a voltage requirement determination and voltage feedback generator module disposed on the integrated circuit and coupled to the performance monitoring module. The voltage requirement determination and voltage feedback generator module is configured to output a feedback voltage signal having a voltage level as a function of at least the indicator.

Abstract: A method for testing an electronic device includes supplying a first voltage output from a voltage regulator to a first power connection terminal of the electronic device to provide power to the electronic device, providing to the voltage regulator a second voltage on a second power connection terminal of the electronic device that is in connection with the first power connection terminal by a first circuit of the electronic device, regulating, using the voltage regulator, the first voltage based on a comparison of the second voltage and a target voltage, and determining whether the electronic device meets a performance requirement while the first voltage is regulated.

Abstract: Aspects of the disclosure provide an integrated circuit (IC) chip that includes a feedback control circuit and a detecting circuit. The feedback control circuit is configured to govern a feedback signal to a first regulator that regulates a first power supply to the IC chip based on the feedback signal. The feedback control circuit is powered at least partially by a second power supply. The detecting circuit is configured to detect a power down of the second power supply, and to cause the feedback control circuit to be disengaged from the feedback signal in response to the power down.

Abstract: Systems and methods are provided for an interposer for coupling two or more integrated circuit dies to a circuit package. A first integrated circuit portion is disposed on a first location of a single semiconductor substrate. A second integrated circuit portion is disposed on a second location of the single semiconductor substrate, where the second integrated circuit portion is electrically isolated from the first integrated circuit portion along a first axis. The first and second integrated circuit portions are configured to provide an electrical coupling to two or more corresponding top die integrated circuits across a second axis that is perpendicular to the first axis.

Abstract: An integrated circuit includes an operational circuit module receiving a supply voltage from a voltage regulator external to the integrated circuit, and an adaptive voltage scaling module to adjust the supply voltage based on performance characteristics of the operational circuit module. The adaptive voltage scaling module can include a performance monitoring module disposed on the integrated circuit and configured to generate at least an indicator corresponding to at least one performance characteristic of the operational circuit module. The adaptive scaling module can include a voltage requirement determination and voltage feedback generator module disposed on the integrated circuit and coupled to the performance monitoring module. The voltage requirement determination and voltage feedback generator module is configured to output a feedback voltage signal having a voltage level as a function of at least the indicator.

Abstract: Aspects of the disclosure provide an integrated circuit (IC). The IC includes an input interface and a controller. The input interface is configured to receive an input signal providing information for controlling a supply voltage based on a performance characteristic of another IC. The controller is configured to generate an output signal for controlling the supply voltage based on a combination of the input signal and a performance characteristic of the IC.

Abstract: Aspects of the disclosure provide an integrated circuit. The integrated circuit includes a first operational circuit module receiving a first supply voltage from a first voltage regulator that is external to the integrated circuit, and a first adaptive voltage scaling module to adjust the first supply voltage based on performance characteristics of the first operational circuit module. In an embodiment of the disclosure, the first adaptive voltage scaling module includes a first performance monitoring module. The performance monitoring module is disposed on the integrated circuit, and is configured to generate at least a first indicator corresponding to at least one performance characteristic of the first operational circuit module. Further, the first adaptive scaling module includes a first voltage requirement determination and voltage feedback generator module that is disposed on the integrated circuit, and is coupled to the first performance monitoring module.

Abstract: Aspects of the disclosure provide a method. The method includes causing a voltage level of a signal transmitted on a transmission line to be non-linearly modified to reduce a voltage variation at a target level, and providing the modified signal to a receiving circuit that is disposed on the transmission line. In an embodiment, the method includes causing the voltage level of the signal transmitted on the transmission line to be non-linearly modified to reduce a first voltage variation at a first target level corresponding to a first digital value and to reduce a second voltage variation at a second target level corresponding to a second digital value.

Abstract: Aspects of the disclosure provide a testing method. The method includes supplying a power supply from a voltage regulator to a device under test (DUT). The DUT includes an adaptive voltage scaling module configured to generate a feedback signal in response to the power supply. Further, the method includes receiving the feedback signal from the DUT to the voltage regulator to regulate the power supply based on the feedback signal from the DUT, and determining whether the DUT meets a specified performance requirement while the voltage regulator regulates the power supply provided to the DUT based on the feedback signal received from the DUT.

Abstract: A voltage level shifting circuit may include a differential first-stage level shifter that receives a binary input signal and generates a non-inverted first-stage shifted output signal and an inverted first-stage shifted output signal, a second-stage level shifter that receives the first-stage shifted output signals and generates a non-inverted second-stage shifted output signal and an inverted second-stage shifted output signal, and a signal generator that generates a level shifted final output signal corresponding to the binary input signal that is based on the non-inverted second-stage shifted output signal and the inverted second-stage shifted output signal. The voltage swing of the first stage output signals may be limited to swing between a non-zero lower value and an upper value that is less than or equal to a source-to-drain voltage rating of transistors in the differential first-stage level shifter.

Abstract: Aspects of the disclosure provide a method for testing an electronic device. The method includes supplying a first voltage output from a voltage regulator to a first power connection terminal of the electronic device to provide power to the electronic device, providing to the voltage regulator a second voltage on a second power connection terminal of the electronic device that is in connection with the first power connection terminal by a first circuit of the electronic device, regulating, using the voltage regulator, the first voltage based on a comparison of the second voltage and a target voltage, and determining whether the electronic device meets a performance requirement while the first voltage is regulated.

Abstract: An isolated level shifter base cell that is configurable as either an isolated HIGH level shifter or an isolated LOW level shifter based on changes to connection layers, e.g., metal-2 and/or via-1 layers, without adjusting lower layers, or base layers, that form the isolated level shifter base cell. Regardless of the configuration selected, the isolated level shifter base cell requires the same footprint and provides the same input-to-output path timing. Further, the isolated level shifter base cell is configurable as either a HIGH or LOW isolation cell, i.e., without level shifting, based on changes to the connection layers while again maintaining the same footprint and input-to-output path timing. The configuration of the described isolated level shifter base cell can be changed late in the integrated circuit design process without affecting integrated circuit base layers, without changing the integrated circuit footprint, and without introducing integrated circuit timing changes.

Abstract: An apparatus and method are disclosed for generating one or more clock signals. A clock signal is generated based on pattern signals and a reference clock signal. When the reference clock signal transitions high, the state of a first pattern signal is output, and when the reference clock signal transitions low, the state of a second pattern signal is output. Successive states of the first and second pattern signals, selected according to the reference clock signal, provide the generated clock signal.

Abstract: A voltage level shifting circuit may include a differential first-stage level shifter that receives a binary input signal and generates a non-inverted first-stage shifted output signal and an inverted first-stage shifted output signal, a second-stage level shifter that receives the first-stage shifted output signals and generates a non-inverted second-stage shifted output signal and an inverted second-stage shifted output signal, and a signal generator that generates a level shifted final output signal corresponding to the binary input signal that is based on the non-inverted second-stage shifted output signal and the inverted second-stage shifted output signal. The voltage swing of the first stage output signals may be limited to swing between a non-zero lower value and an upper value that is less than or equal to a source-to-drain voltage rating of transistors in the differential first-stage level shifter.

Abstract: Aspects of the disclosure provide a circuit using digital techniques to generate a differential signal with a low skew. The circuit can include a first switching element configured to receive at least a first logic value and a second logic value, and output a first signal of the differential signal, the second logic value being different from the first logic value. Further, the circuit can include a second switching element configured to receive at least the first logic value and the second logic value, and output a second signal of the differential signal.

Abstract: An apparatus and method are disclosed for generating one or more clock signals. A clock signal is generated based on pattern signals and a reference clock signal. When the reference clock signal transitions high, the state of a first pattern signal is output, and when the reference clock signal transitions low, the state of a second pattern signal is output. Successive states of the first and second pattern signals, selected according to the reference clock signal, provide the generated clock signal.

Abstract: A digitally controlled capacitor includes a first set of N capacitors, wherein the first set has a first capacitance value and each of the M capacitors has a second capacitance value, and at least one second set of N capacitors. The second set has the first capacitance value and each of the N capacitors has a third capacitance value that is greater than the second capacitance value. M and N are integers greater than one and M is not equal to N.