Patents by Inventor Ignazio Antonino Urzi

Ignazio Antonino Urzi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10255207
    Abstract: A system is configured to capture a set of interrupts and output the interrupts serially onto an interconnect. The interrupts, which are routed to a destination, may first be packetized such that additional information is associated with the interrupt within the packet.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: April 9, 2019
    Assignees: STMicroelectronics (Research & Development) Limited, STMicroelectronics (Grenoble 2) SAS
    Inventors: Davide Sarta, Ignazio Antonino Urzi
  • Patent number: 10102171
    Abstract: A system, such as a System-on-Chip includes an interface component or PLUG which generates transactions over an IP block, such as an interconnect serving one or more clients via virtual channels. The client or clients are mapped onto the virtual channels via client/virtual channel mappings. The virtual channels are provided as a first set of virtual channels in the interface component which cooperate with a second set of virtual channels in the IP block. First and second client/virtual channel mappings for the first set of virtual channels and the second set of virtual channels are provided. The first and second client/virtual channel mappings are separately programmable and mutually decoupled from one another.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: October 16, 2018
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMIcroelectronics S.r.l.
    Inventors: Daniele Mangano, Ignazio Antonino Urzi
  • Patent number: 10019399
    Abstract: A system for designing Network-on-Chip interconnect arrangements includes a Network-on-Chip backbone with a plurality of backbone ports and a set of functional clusters of aggregated IPs providing respective sets of System-on-Chip functions. The functional clusters include respective sub-networks attachable to any of the backbone ports and to any other functional cluster in the set of functional clusters independently of the source map of the Network-on-Chip backbone.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: July 10, 2018
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics S.R.L.
    Inventors: Daniele Mangano, Ignazio Antonino Urzi
  • Publication number: 20170270070
    Abstract: A system, such as a System-on-Chip includes an interface component or PLUG which generates transactions over an IP block, such as an interconnect serving one or more clients via virtual channels. The client or clients are mapped onto the virtual channels via client/virtual channel mappings. The virtual channels are provided as a first set of virtual channels in the interface component which cooperate with a second set of virtual channels in the IP block. First and second client/virtual channel mappings for the first set of virtual channels and the second set of virtual channels are provided. The first and second client/virtual channel mappings are separately programmable and mutually decoupled from one another.
    Type: Application
    Filed: May 30, 2017
    Publication date: September 21, 2017
    Inventors: Daniele Mangano, Ignazio Antonino Urzi
  • Patent number: 9697161
    Abstract: A system, such as a System-on-Chip includes an interface component or PLUG which generates transactions over an IP block, such as an interconnect serving one or more clients via virtual channels. The client or clients are mapped onto the virtual channels via client/virtual channel mappings. The virtual channels are provided as a first set of virtual channels in the interface component which cooperate with a second set of virtual channels in the IP block. First and second client/virtual channel mappings for the first set of virtual channels and the second set of virtual channels are provided. The first and second client/virtual channel mappings are separately programmable and mutually decoupled from one another.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: July 4, 2017
    Assignees: STMICROELECTRONICS (GRENOBLE) SAS, STMICROELECTRONICS S.R.L.
    Inventors: Daniele Mangano, Ignazio Antonino Urzi
  • Patent number: 9419952
    Abstract: A method for managing an operation of an encrypted global interleaved memory space physically implemented according to an interleaving addressing scheme in encrypted memory banks of a plurality of memories respectively belonging to a plurality of channels. The method includes providing each channel with a local address pointer configured to be incrementally moved along the global memory space each time the global memory space is addressed at the current address pointed by the pointer, and in an absence of movement of the local pointer of a channel during a time period, addressing the global memory space from the channel through the address interleaving with a specific transaction at the current address, and upon reception at the channel of the specific transaction having been initiated by the channel, re-encrypting data located at the current address with a new encryption key and incrementing the local address pointer to its next position.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: August 16, 2016
    Assignees: STMICROELECTRONICS (GRENOBLE 2) SAS, STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Ignazio Antonino Urzi, Asif Rashid Zargar
  • Patent number: 9389979
    Abstract: A system includes a processor and a plurality of circuits connected through an interconnection network, wherein associated to each circuit is a respective communication interface configured for exchanging data between the respective circuit and the interconnection network. In particular, a debug unit is associated with each communication interface. Each debug unit is configurable as a data-insertion point, wherein the debug unit transmits data by means of the respective communication interface to the interconnection network, or each debug unit is configurable as a data-reception point, wherein the debug unit receives data by means of the respective communication interface from the interconnection network.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: July 12, 2016
    Assignees: STMICROELECTRONICS (GRENOBLE 2) SAS, STMICROELECTRONICS S.R.L.
    Inventors: Daniele Mangano, Ignazio Antonino Urzi
  • Publication number: 20160070667
    Abstract: A system for designing Network-on-Chip interconnect arrangements includes a Network-on-Chip backbone with a plurality of backbone ports and a set of functional clusters of aggregated IPs providing respective sets of System-on-Chip functions. The functional clusters include respective sub-networks attachable to any of the backbone ports and to any other functional cluster in the set of functional clusters independently of the source map of the Network-on-Chip backbone.
    Type: Application
    Filed: November 12, 2015
    Publication date: March 10, 2016
    Inventors: Daniele Mangano, Ignazio Antonino Urzi
  • Publication number: 20150358300
    Abstract: A method for managing an operation of an encrypted global interleaved memory space physically implemented according to an interleaving addressing scheme in encrypted memory banks of a plurality of memories respectively belonging to a plurality of channels. The method includes providing each channel with a local address pointer configured to be incrementally moved along the global memory space each time the global memory space is addressed at the current address pointed by the pointer, and in an absence of movement of the local pointer of a channel during a time period, addressing the global memory space from the channel through the address interleaving with a specific transaction at the current address, and upon reception at the channel of the specific transaction having been initiated by the channel, re-encrypting data located at the current address with a new encryption key and incrementing the local address pointer to its next position.
    Type: Application
    Filed: March 12, 2015
    Publication date: December 10, 2015
    Inventors: Ignazio Antonino URZI, Asif Rashid Zargar
  • Patent number: 9202002
    Abstract: A system for designing Network-on-Chip interconnect arrangements includes a Network-on-Chip backbone with a plurality of backbone ports and a set of functional clusters of aggregated IPs providing respective sets of System-on-Chip functions. The functional clusters include respective sub-networks attachable to any of the backbone ports and to any other functional cluster in the set of functional clusters independently of the source map of the Network-on-Chip backbone.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: December 1, 2015
    Assignees: STMICROELECTRONICS (GRENOBLE 2) SAS, STMICROELECTRONICS S.R.L.
    Inventors: Daniele Mangano, Ignazio Antonino Urzi
  • Patent number: 9178776
    Abstract: A method includes providing at least one target bandwidth for bandwidth usage on an interconnect, the target bandwidth being for traffic associated with a traffic initiator. The method also includes measuring a served bandwidth and resetting the measuring of served bandwidth in response to an occurrence of an event.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: November 3, 2015
    Assignees: STMICROELECTRONICS (GRENOBLE 2) SAS, STMICROELECTRONICS S.R.L.
    Inventors: Ignazio Antonino Urzi, Rene Peyrard, Daniele Mangano
  • Patent number: 9100354
    Abstract: A system comprises a resource, such as an interconnection, for example, of the Network-on-Chip (NoC) type, having an overall bandwidth available for allocation to a set of initiators that compete for allocation of the overall bandwidth. The system includes a communication arbiter for allocating the overall bandwidth to the initiators according to respective values of bandwidth requested (RBW) by the initiators. A control device (50) is configured to detect the deviation between the value of bandwidth allocated to the initiators and the respective value of requested bandwidth and allocate the overall bandwidth to the initiators in a dynamic way minimizing the mean value of the deviation.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: August 4, 2015
    Assignees: STMICROELECTRONICS SRL, STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Daniele Mangano, Ignazio Antonino Urzi, Giovanni Strano
  • Publication number: 20150127865
    Abstract: A system is configured to capture a set of interrupts and output the interrupts serially onto an interconnect. The interrupts, which are routed to a destination, may first be packetized such that additional information is associated with the interrupt within the packet.
    Type: Application
    Filed: November 7, 2014
    Publication date: May 7, 2015
    Inventors: Davide Sarta, Ignazio Antonino Urzi
  • Patent number: 9026761
    Abstract: An interface system for interfacing an asynchronous circuit with a synchronous circuit, wherein the synchronous circuit samples, in response to a clock signal, a first data signal when a first control signal indicates that the first data signal contains valid data, and wherein the asynchronous circuit generates a second data signal according to an asynchronous communication protocol. The system includes a FIFO memory, a control circuit for asynchronously writing the second data signal in the memory when the second data signal indicates the start of a communication, and synchronously reading the second data signal from the memory in response to a clock signal, and a conversion circuit for decoding, according to a asynchronous communication protocol, the second data signal read from the memory in a decoded data signal, wherein the decoded data signal corresponds to the first data signal.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: May 5, 2015
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics S.R.L.
    Inventors: Daniele Mangano, Salvatore Pisasale, Ignazio Antonino Urzi'
  • Publication number: 20150106778
    Abstract: A system for designing Network-on-Chip interconnect arrangements includes a Network-on-Chip backbone with a plurality of backbone ports and a set of functional clusters of aggregated IPs providing respective sets of System-on-Chip functions. The functional clusters include respective sub-networks attachable to any of the backbone ports and to any other functional cluster in the set of functional clusters independently of the source map of the Network-on-Chip backbone.
    Type: Application
    Filed: October 9, 2014
    Publication date: April 16, 2015
    Inventors: Daniele Mangano, Ignazio Antonino Urzi
  • Patent number: 8873668
    Abstract: A circuit includes a first n-bit communications block and a second m-bit communications block. A controller is configured to control mode of operation for the first and second communications blocks. In a first mode, the first and second communications blocks function as a single communications block for n+m bit communications. In a second mode, the first and second communications blocks operate as substantially independent communications block for n bit communications and m bit communications.
    Type: Grant
    Filed: October 15, 2012
    Date of Patent: October 28, 2014
    Assignees: STMicroelectronics SA, STMicroelectronics (Research & Development) Limited, STMicroelectronics (Grenoble 2) SAS
    Inventors: Andrew Ferris, Ignazio Antonino Urzi, Pascal Teissier
  • Publication number: 20140289439
    Abstract: A system, such as a System-on-Chip includes an interface component or PLUG which generates transactions over an IP block, such as an interconnect serving one or more clients via virtual channels. The client or clients are mapped onto the virtual channels via client/virtual channel mappings. The virtual channels are provided as a first set of virtual channels in the interface component which cooperate with a second set of virtual channels in the IP block. First and second client/virtual channel mappings for the first set of virtual channels and the second set of virtual channels are provided. The first and second client/virtual channel mappings are separately programmable and mutually decoupled from one another.
    Type: Application
    Filed: March 19, 2014
    Publication date: September 25, 2014
    Applicants: STMicroelectronics S.r.I, STMicroelectronics (Grenoble 2) SAS
    Inventors: Daniele Mangano, Ignazio Antonino Urzi
  • Patent number: 8831160
    Abstract: An apparatus includes a first clock source, a second clock source and circuitry configured to supply a clock signal to a circuit. The circuitry operates to change the clock signal from one frequency to another different frequency. This change is made in a manner whereby no clock signal is supplied during a period of time when the change from the one frequency to the another different clock frequency is being made.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: September 9, 2014
    Assignees: STMicroelectronics (Research & Development) Limited, STMicroelectronics (Grenoble 2) SAS
    Inventors: Andrew Ferris, Ignazio Antonino Urzi
  • Patent number: 8780935
    Abstract: A communication system includes interfacing between a first synchronous circuit and a second synchronous circuit. The system includes a first interface system and a second interface system. The first interface system receives data from the first synchronous circuit, and encodes the data according to an asynchronous communication protocol. The encoded data are transmitted over a communication channel to the second interface system. The second interface system decodes the data and transmits the decoded data to the second synchronous circuit. The first interface system includes a first FIFO memory for storing temporarily the data received from the first synchronous circuit and the second interface system includes a second FIFO memory for storing temporarily the data transmitted over the communication channel.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: July 15, 2014
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics, S.r.l.
    Inventors: Daniele Mangano, Ignazio Antonino Urziā€²
  • Patent number: 8782302
    Abstract: A node having a node input is configured to receive a plurality of transactions intended for a plurality of different targets. The node has multiple node outputs. At least one target is provided, that target including an input configured to receive a respective output of the node. The node is configured to direct transactions to the at least one target or an output (for passing to a different partition) depending on whether the transactions are intended for the target or a different target. This determination is made in response to a conversion operation which converts a target address of the transaction to an identification associated with the target or the output.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: July 15, 2014
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics Srl
    Inventors: Ignazio Antonino Urzi, Philippe D'Audigier, Daniele Mangano