Patents by Inventor Ignazio Bellomo
Ignazio Bellomo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8415978Abstract: A state machine for generating signals configured for generating different signals according to the current state of the machine. The state machine is configured to change state both as a function of an internal timer and as a function of signals representative of events external to the state machine.Type: GrantFiled: December 22, 2009Date of Patent: April 9, 2013Assignees: STMicroelectronics s.r.l., STMicroelectronics Design and Application s.r.o.Inventors: Ales Loidl, Ignazio Bellomo, Luca Giussani, David Vincenzoni
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Publication number: 20100168873Abstract: A state machine for generating signals configured for generating different signals according to the current state of the machine. The state machine is configured to change state both as a function of an internal timer and as a function of signals representative of events external to the state machine.Type: ApplicationFiled: December 22, 2009Publication date: July 1, 2010Applicants: STMICROELECTRONICS s.r. l., STMICROELECTRONICS DESIGN and APPLICATION s.r. o.Inventors: Ales LOIDL, Ignazio Bellomo, Luca Giussani, David Vincenzoni
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Patent number: 7084790Abstract: A device for effectuating a digital estimate of a periodic electric signal is described. The device comprising a linear DAC having an output signal, a comparator that compares the output signal of the linear DAC with the periodic electric signal, and logic circuitry having in input the output signal of the comparator and a pulse clock signal. The logic circuitry provides a first digital signal in input to the linear DAC and a second digital signal representative of the estimate of the periodic electric signal.Type: GrantFiled: December 7, 2004Date of Patent: August 1, 2006Assignee: STMicroelectronics S.r.l.Inventors: Antonio Borrello, Stefano Saggini, Aldo Novelli, Ignazio Bellomo
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Patent number: 7062159Abstract: A device for correcting a digital estimate of an electric signal is described. The device includes a comparator that generates a current proportional to the difference between an analog estimate signal, which derives from the digital estimate, and the electric signal. The device also includes a capacitor positioned to be charged by the current, a transistor that discharges the capacitor, and a comparator that compares the voltage at the terminal of the capacitor with a reference voltage. The device also includes a controller that drives the transistor in response to the output signal of the comparator and a logic device that generates a correction digital signal to be added to or subtracted from the digital estimate of the electric signal in correspondence of an ascending or descending waveform of the electric signal.Type: GrantFiled: December 7, 2004Date of Patent: June 13, 2006Assignee: STMicroelectronics S.r.l.Inventors: Antonio Borrello, Stefano Saggini, Aldo Novelli, Ignazio Bellomo
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Publication number: 20060120699Abstract: A device for correcting a digital estimate of an electric signal is described. The device includes a comparator that generates a current proportional to the difference between an analog estimate signal, which derives from the digital estimate, and the electric signal. The device also includes a capacitor positioned to be charged by the current, a transistor that discharges the capacitor, and a comparator that compares the voltage at the terminal of the capacitor with a reference voltage. The device also includes a controller that drives the transistor in response to the output signal of the comparator and a logic device that generates a correction digital signal to be added to or subtracted from the digital estimate of the electric signal in correspondence of an ascending or descending waveform of the electric signal.Type: ApplicationFiled: December 7, 2004Publication date: June 8, 2006Applicant: STMicroelectronics S.r.l.Inventors: Antonio Borrello, Stefano Saggini, Aldo Novelli, Ignazio Bellomo
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Publication number: 20060119495Abstract: A device for effectuating a digital estimate of a periodic electric signal is described. The device comprising a linear DAC having an output signal, a comparator that compares the output signal of the linear DAC with the periodic electric signal, and logic circuitry having in input the output signal of the comparator and a pulse clock signal. The logic circuitry provides a first digital signal in input to the linear DAC and a second digital signal representative of the estimate of the periodic electric signal.Type: ApplicationFiled: December 7, 2004Publication date: June 8, 2006Applicant: STMicroelectronics S.r.l.Inventors: Antonio Borrello, Stefano Saggini, Aldo Novelli, Ignazio Bellomo
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Patent number: 6772379Abstract: An apparatus for verifying the data retention in a non-volatile memory is described which comprises at least one multiplexer and at least one shift register. The multiplexer and the at least one shift register are disposed so that the data of the non-volatile memory are in input to the multiplexer the output of which is in turn in input to the at least one shift register. The apparatus comprises a logical circuitry which by suitable commands controls the data transfer from said multiplexer to said at least one shift register, the data loading and the output data shifting in said at least one shift register.Type: GrantFiled: November 10, 2000Date of Patent: August 3, 2004Assignee: STMicroelectronics S.r.l.Inventors: Alessandro Camera, Ignazio Bellomo, Paolo Sandri
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Patent number: 6630854Abstract: The present invention relates a monostable circuit adapted to provide a delay having a length inversely proportional to an input signal, characterized by comprising generating means (21, 22) adapted to generate a signal proportionally to an input signal (Vin) and to a corrective factor (35), comparing means (23) adapted to compare the value of said signal with a prefixed value range (Imin, Imax) and correcting means (24) adapted to correct said corrective factor (35) in the case that the value of said signal is out of said prefixed value range (Imin, Imax).Type: GrantFiled: January 14, 2002Date of Patent: October 7, 2003Assignee: STMicroelectronics S.r.l.Inventors: Giulio Corva, Ignazio Bellomo
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Patent number: 6538479Abstract: A driver circuit drives at least one power switch, which circuit comprises a final stage including a complementary pair of power transistors connected to said switch at a common output node. Advantageously, this circuit comprises a respective power-on buffer stage, connected in upstream of each of the power transistors, and a power-on detector associated with each power transistor, the detector associated with one of the power transistors being connected to the buffer stage of the complementary one of the transistors to prevent the power transistors from being turned on simultaneously.Type: GrantFiled: August 28, 2001Date of Patent: March 25, 2003Assignee: STMicroelectronics S.r.l.Inventors: Ignazio Bellomo, Giulio Corva, Francesco Villa
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Publication number: 20030015999Abstract: The present invention relates a monostable circuit adapted to provide a delay having a length inversely proportional to an input signal, characterized by comprising generating means (21, 22) adapted to generate a signal proportionally to an input signal (Vin) and to a corrective factor (35), comparing means (23) adapted to compare the value of said signal with a prefixed value range (Imin, Imax) and correcting means (24) adapted to correct said corrective factor (35) in the case that the value of said signal is out of said prefixed value range (Imin, Imax).Type: ApplicationFiled: January 14, 2002Publication date: January 23, 2003Inventors: Giulio Corva, Ignazio Bellomo
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Patent number: 6424557Abstract: An integrated device comprises at least one circuit element and a plurality of trimming elements which can be connected selectively to the at least one circuit element in order to achieve a predetermined tolerance of a characteristic parameter of the at least one circuit element; the integrated device includes a plurality of electronic switches, each of which can be switched between a first state and a second state in which it activates and deactivates a corresponding one of the trimming elements, respectively, and a memory for storing an indication of the states of the electronic switches and for operating each electronic switch in the first state or in the second state according to the indication stored.Type: GrantFiled: November 30, 2000Date of Patent: July 23, 2002Assignee: STMicroelectronics S.r.l.Inventors: Alessandro Camera, Paolo Sandri, Ignazio Bellomo, Filippo Marino
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Patent number: 6396251Abstract: The invention relates to a control circuit for a hysteretic switching voltage regulator, which comprises a logic circuit driving an output stage; a hysteresis comparator comparing the voltage value at the output of the regulator with a reference voltage; a current sensor for sensing, through a comparator, the current drain of a load connected to the output of the regulator. This control circuit further comprises a device for adjusting the hysteresis range of the hysteresis comparator, and a hysteresis frequency sensing and controlling logic portion connected to the output of the hysteresis comparator, the logic portion acting on the frequency adjusting device.Type: GrantFiled: March 6, 2001Date of Patent: May 28, 2002Assignee: STMicroelectronics S.r.l.Inventors: Giulio Corva, Alessandro Camera, Ignazio Bellomo
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Patent number: 6381185Abstract: A method for testing a programmable, nonvolatile memory including a matrix of memory cells is provided. A plurality of memory cells are programmed. The programmed memory cells are addressed in succession to identify a lowest of threshold voltage levels. The addressing for each memory location includes applying a selection voltage that is lower than the lowest threshold voltage level corresponding to a memory location currently being addressed. The bits are read from the programmed memory cells for the memory location currently being addressed. The reading is repeated while progressively changing the selection voltage supplied to the word line corresponding to the memory location currently being addressed until it is detected that at least one of the bits of the memory location currently being addressed has switched from a first logic level corresponding to a reading of a programmed memory cell to a second logic level corresponding to a reading of a non-programmed memory cell.Type: GrantFiled: February 14, 2001Date of Patent: April 30, 2002Assignee: STMicroelectronics S.r.l.Inventors: Alessandro Camera, Paolo Sandri, Ignazio Bellomo, Albino Pidutti
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Publication number: 20020030516Abstract: A driver circuit drives at least one power switch, which circuit comprises a final stage including a complementary pair of power transistors connected to said switch at a common output node. Advantageously, this circuit comprises a respective power-on buffer stage, connected in upstream of each of the power transistors, and a power-on detector associated with each power transistor, the detector associated with one of the power transistors being connected to the buffer stage of the complementary one of the transistors to prevent the power transistors from being turned on simultaneously.Type: ApplicationFiled: August 28, 2001Publication date: March 14, 2002Applicant: STMicroelectronics S.r.l.Inventors: Ignazio Bellomo, Giulio Corva, Francesco Villa
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Publication number: 20010038278Abstract: The invention relates to a control circuit for a hysteretic switching voltage regulator, which comprises a logic circuit driving an output stage; a hysteresis comparator comparing the voltage value at the output of the regulator with a reference voltage; a current sensor for sensing, through a comparator, the current drain of a load connected to the output of the regulator. This control circuit further comprises a device for adjusting the hysteresis range of the hysteresis comparator, and a hysteresis frequency sensing and controlling logic portion connected to the output of the hysteresis comparator, the logic portion acting on the frequency adjusting device.Type: ApplicationFiled: March 6, 2001Publication date: November 8, 2001Inventors: Giulio Corva, Alessandro Camera, Ignazio Bellomo
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Publication number: 20010015925Abstract: A method for testing a programmable, non-volatile memory including a matrix of memory cells is provided. A plurality of memory cells are programmed. The programmed memory cells are addressed in succession to identify a lowest of threshold voltage levels. The addressing for each memory location includes applying a selection voltage that is lower than the lowest threshold voltage level corresponding to a memory location currently being addressed. The bits are read from the programmed memory cells for the memory location currently being addressed. The reading is repeated while progressively changing the selection voltage supplied to the word line corresponding to the memory location currently being addressed until it is detected that at least one of the bits of the memory location currently being addressed has switched from a first logic level corresponding to a reading of a programmed memory cell to a second logic level corresponding to a reading of a non-programmed memory cell.Type: ApplicationFiled: February 14, 2001Publication date: August 23, 2001Applicant: STMicroelectronics S.r. I.Inventors: Alessandro Camera, Paolo Sandri, Ignazio Bellomo, Albino Pidutti
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Publication number: 20010013633Abstract: An integrated device comprises at least one circuit element and a plurality of trimming elements which can be connected selectively to the at least one circuit element in order to achieve a predetermined tolerance of a characteristic parameter of the at least one circuit element; the integrated device includes a plurality of electronic switches, each of which can be switched between a first state and a second state in which it activates and deactivates a corresponding one of the trimming elements, respectively, and means for storing an indication of the states of the electronic switches and for operating each electronic switch in the first state or in the second state according to the indication stored.Type: ApplicationFiled: November 30, 2000Publication date: August 16, 2001Inventors: Alessandro Camera, Paolo Sandri, Ignazio Bellomo, Filippo Marino