Patents by Inventor Igor Arsovski

Igor Arsovski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7403039
    Abstract: A multimode circuit that is configured to operate in one of multiple operating modes is disclosed. In particular, an exemplary multimode circuit may be configured to operating in one of a full-swing mode, a limited-swing mode, a full-swing to limited-swing converter mode, and a limited-swing to full-swing converter mode. The operating modes of the multimode circuit may be dynamically selectable. One or more multimode circuits may be part of a configurable distribution path for controlling the performance of a signal distribution path or tree of an integrated circuit.
    Type: Grant
    Filed: February 2, 2007
    Date of Patent: July 22, 2008
    Assignee: International Business Machines Corporation
    Inventors: Igor Arsovski, Anthony R. Bonaccio, Hayden C. Cranford, Jr., Joseph A. Iadanza, Pradeep Thiagarajan, Sebastian T. Ventrone
  • Patent number: 7362138
    Abstract: A multimode circuit that is configured to operate in one of multiple operating modes is disclosed. In particular, an exemplary multimode circuit may be configured to operating in one of a full-swing mode, a limited-swing mode, a full-swing to limited-swing converter mode, and a limited-swing to full-swing converter mode. The operating modes of the multimode circuit may be dynamically selectable. One or more multimode circuits may be part of a configurable distribution path for controlling the performance of a signal distribution path or tree of an integrated circuit.
    Type: Grant
    Filed: December 20, 2006
    Date of Patent: April 22, 2008
    Assignee: International Business Machines Corporation
    Inventors: Igor Arsovski, Anthony R. Bonaccio, Hayden C. Cranford, Jr., Joseph A. Iadanza, Pradeep Thiagarajan, Sebastian T. Ventrone
  • Publication number: 20080080223
    Abstract: This patent describes a method for switching search-lines in a Content Addressable Memory (CAM) asynchronously to improve CAM speed and reduce CAM noise without affecting its power performance. This is accomplished by resetting the match-lines prior to initiating a search and then applying a search word to the search-lines. A reference match-line is provided to generate the timing for the search operation and provide the timing for the asynchronous application of the search data on the SLs.
    Type: Application
    Filed: September 15, 2006
    Publication date: April 3, 2008
    Inventors: Igor Arsovski, Rahul K. Nadkarni, Reid A. Wistort
  • Publication number: 20080065923
    Abstract: A method, system and computer program product reducing clock noise generated by clock signals in an integrated circuit (IC) are disclosed. Conventional IC design attempts to ensure coincident clock active edge arrival times for all clocked elements. The coincident active clock edges generate coincident noise currents, which elevates the total noise current. The current invention assigns clock arrival times for clocked elements of an IC based on a desired clock arrival time distribution such that active clock edges are not coincident. As a consequence, the total noise would be spread over a large portion of the clock cycle, thus reducing the noise magnitude substantially.
    Type: Application
    Filed: September 11, 2006
    Publication date: March 13, 2008
    Inventors: Igor Arsovski, Joseph A. Iadanza, Jason M. Norman, Sebastian T. Ventrone
  • Publication number: 20080046789
    Abstract: This patent describes a method for varying the amplitude and frequency of power supply oscillations produced by content addressable memories or other critical circuits using BIST. Supply oscillations are produced by performing noisy (high switching activity—high current demand) searches followed by quiet (low switching activity—low current demand) searches. The amplitude and frequency of oscillations can be varied by changing the number of noisy and quiet searches e.g. pattern 1-noisy quiet, noisy, quiet; pattern 2-noisy, noisy, quiet, noisy, noisy, quiet, etc. By going through different patterns the current demand from the CAM macro increases the likelihood of producing worst—case noise and enables testing of CAM operation as well as surrounding circuitry in these noisy conditions.
    Type: Application
    Filed: August 21, 2006
    Publication date: February 21, 2008
    Inventors: Igor Arsovski, Valerie Chickanosky, Rahul Nadkarni, Michael Oucllette, Reid Wistort
  • Publication number: 20080046772
    Abstract: A method and system for reducing clock noises are disclosed. A clock signal includes active edges and inactive edges. Inactive edges produce clock noise but are not critical to the functionality of the clock signal. That is, only active edges are critical to proper timing of an integrated circuit (IC). As such, inactive edges of clock signals to clocked elements of an IC may be shifted to be misaligned to one another. As a consequence, peak noise produced by the inactive edges will be spread over a large area and therefore will be reduced in amplitude.
    Type: Application
    Filed: July 17, 2006
    Publication date: February 21, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Igor Arsovski, Joseph A. Iadanza, Jason M. Norman, Hemen Shah, Sebastian T. Ventrone
  • Publication number: 20080043890
    Abstract: A method for noise comprising synthesizing blocks of sequential latches, e.g., a pipeline circuit architecture or clocking domain, which comprises combinational logic, synthesizing a root or a master clock and at least one phase-shifted sub-domain clock for each block, assigning primary inputs and primary outputs of the block to the root clock, assigning non-primary inputs and non-primary outputs of the block to the sub-domain clock, splitting root clock inputs into root clock inputs and phase-shifted sub-domain clock inputs, assigning each of the blocks a different phase-shifted sub-domain clock phase offset, creating a clock generation circuitry for the root clocks and the phase-shifted sub-domain clocks.
    Type: Application
    Filed: July 26, 2006
    Publication date: February 21, 2008
    Inventors: Igor Arsovski, Serafino Bueti, Joseph A. Iadanza, Jason M. Norman, Hemen R. Shah, Sebastian T. Ventrone
  • Publication number: 20080030223
    Abstract: A system and method for eliminating step response power supply perturbation during voltage island power-up/power-down on an integrated circuit is disclosed. An IC chip communicates with a primary power supply and includes at least one voltage island. A primary header on the voltage island of the chip communicates with the primary power supply via a primary header power path. A secondary header on the voltage island of the chip communicates with a secondary power supply via a secondary header power path. A control decoder communicating with the IC chip and the voltage island regulates the state of the primary and secondary headers.
    Type: Application
    Filed: August 2, 2006
    Publication date: February 7, 2008
    Inventors: Igor Arsovski, Joseph A. Iadanza
  • Publication number: 20080030254
    Abstract: A design structure for eliminating step response power supply perturbation during voltage island power-up/power-down on an integrated circuit is disclosed. An IC chip communicates with a primary power supply and includes at least one voltage island. A primary header on the voltage island of the chip communicates with the primary power supply via a primary header power path. A secondary header on the voltage island of the chip communicates with a secondary power supply via a secondary header power path. A control decoder communicating with the IC chip and the voltage island regulates the state of the primary and secondary headers.
    Type: Application
    Filed: August 30, 2007
    Publication date: February 7, 2008
    Inventors: Igor Arsovski, Joseph Iadanza
  • Publication number: 20080025074
    Abstract: A design structure for designing, manufacturing, or testing a content addressable memory (CAM) device. The CAM device includes a plurality of CAM cells, match-lines (MLs), search lines, and ML sense amplifiers. The ML sense amplifiers are capable of self-calibration to their respective thresholds to reduce effects of random device variation between adjacent sense amplifiers.
    Type: Application
    Filed: June 15, 2007
    Publication date: January 31, 2008
    Inventor: Igor Arsovski
  • Publication number: 20080025073
    Abstract: A content addressable memory (CAM) device and process for searching a CAM. The CAM device includes a plurality of CAM cells, match-lines (MLs), search lines, and ML sense amplifiers. The ML sense amplifiers are capable of self-calibration to their respective thresholds to reduce effects of random device variation between adjacent sense amplifiers.
    Type: Application
    Filed: July 14, 2006
    Publication date: January 31, 2008
    Inventor: Igor Arsovski
  • Publication number: 20070206397
    Abstract: A low power matchline sensing scheme where power is distributed according to the number of mismatching bits occurring on a matchline is disclosed. In particular, match decisions involving a larger number of mismatched bits consume less power compared to match decisions having a lesser number of mismatched bits. The low power matchline sensing scheme is based upon a precharge-to-miss sensing architecture, and includes a current control circuit coupled to each matchline of the content addressable memory array for monitoring the voltage level of the matchline during a search operation. The current control circuit provides a voltage control signal to the current source of the matchline to adjust the amount of current applied to the matchline in response to the voltage of the matchline. In otherwords, matchlines that are slow to reach the match threshold voltage due to the presence of one or more mismatching bits will receive less current than matchlines having no mismatching bits.
    Type: Application
    Filed: May 11, 2007
    Publication date: September 6, 2007
    Applicant: MOSAID TECHNOLOGIES INCORPORATED
    Inventors: Igor ARSOVSKI, Ali SHEIKHOLESLAMI
  • Patent number: 7227766
    Abstract: A low power matchline sensing scheme where power is distributed according to the number of mismatching bits occurring on a matchline is disclosed. In particular, match decisions involving a larger number of mismatched bits consume less power compared to match decisions having a lesser number of mismatched bits. The low power matchline sensing scheme is based upon a precharge-to-miss sensing architecture, and includes a current control circuit coupled to each matchline of the content addressable memory array for monitoring the voltage level of the matchline during a search operation. The current control circuit provides a voltage control signal to the current source of the matchline to adjust the amount of current applied to the matchline in response to the voltage of the matchline. In otherwords, matchlines that are slow to reach the match threshold voltage due to the presence of one or more mismatching bits will receive less current than matchlines having no mismatching bits.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: June 5, 2007
    Assignee: MOSAID Technologies Incorporated
    Inventors: Igor Arsovski, Ali Sheikholeslami
  • Patent number: 7218135
    Abstract: An integrated circuit device includes functional logic, an anti-noise machine, and state monitoring points providing the anti-noise machine with an interface to the functional logic for monitoring states of the functional logic. The anti-noise machine includes indicia defining noise precursor states for the functional logic, and recognition logic coupled to the state monitoring points. The anti-noise machine is operable to generate anti-noise responsive to the recognition logic detecting in the functional logic noise precursor states matching the indicia.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: May 15, 2007
    Assignee: International Business Machines Corporation
    Inventors: Igor Arsovski, Hayden C. Cranford, Jr., Joseph A. Iadanza, Sebastian T. Ventrone
  • Publication number: 20070075731
    Abstract: An integrated circuit device includes functional logic, an anti-noise machine, and state monitoring points providing the anti-noise machine with an interface to the functional logic for monitoring states of the functional logic. The anti-noise machine includes indicia defining noise precursor states for the functional logic, and recognition logic coupled to the state monitoring points. The anti-noise machine is operable to generate anti-noise responsive to the recognition logic detecting in the functional logic noise precursor states matching the indicia.
    Type: Application
    Filed: September 30, 2005
    Publication date: April 5, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Igor Arsovski, Hayden Cranford, Joseph Iadanza, Sebastian Ventrone
  • Publication number: 20060104100
    Abstract: A low power matchline sensing scheme where power is distributed according to the number of mismatching bits occurring on a matchline is disclosed. In particular, match decisions involving a larger number of mismatched bits consume less power compared to match decisions having a lesser number of mismatched bits. The low power matchline sensing scheme is based upon a precharge-to-miss sensing architecture, and includes a current control circuit coupled to each matchline of the content addressable memory array for monitoring the voltage level of the matchline during a search operation. The current control circuit provides a voltage control signal to the current source of the matchline to adjust the amount of current applied to the matchline in response to the voltage of the matchline. In otherwords, matchlines that are slow to reach the match threshold voltage due to the presence of one or more mismatching bits will receive less current than matchlines having no mismatching bits.
    Type: Application
    Filed: December 30, 2005
    Publication date: May 18, 2006
    Inventors: Igor Arsovski, Ali Sheikholeslami
  • Patent number: 7006368
    Abstract: A low power matchline sensing scheme where power is distributed according to the number of mismatching bits occurring on a matchline is disclosed. In particular, match decisions involving a larger number of mismatched bits consume less power compared to match decisions having a lesser number of mismatched bits. The low power matchline sensing scheme is based upon a precharge-to-miss sensing architecture, and includes a current control circuit coupled to each matchline of the content addressable memory array for monitoring the voltage level of the matchline during a search operation. The current control circuit provides a voltage control signal to the current source of the matchline to adjust the amount of current applied to the matchline in response to the voltage of the matchline. In otherwords, matchlines that are slow to reach the match threshold voltage due to the presence of one or more mismatching bits will receive less current than matchlines having no mismatching bits.
    Type: Grant
    Filed: November 7, 2003
    Date of Patent: February 28, 2006
    Assignee: MOSAID Technologies Incorporated
    Inventors: Igor Arsovski, Ali Sheikholeslami
  • Publication number: 20040145934
    Abstract: A low power matchline sensing scheme where power is distributed according to the number of mismatching bits occurring on a matchline is disclosed. In particular, match decisions involving a larger number of mismatched bits consume less power compared to match decisions having a lesser number of mismatched bits. The low power matchline sensing scheme is based upon a precharge-to-miss sensing architecture, and includes a current control circuit coupled to each matchline of the content addressable memory array for monitoring the voltage level of the matchline during a search operation. The current control circuit provides a voltage control signal to the current source of the matchline to adjust the amount of current applied to the matchline in response to the voltage of the matchline. In otherwords, matchlines that are slow to reach the match threshold voltage due to the presence of one or more mismatching bits will receive less current than matchlines having no mismatching bits.
    Type: Application
    Filed: November 7, 2003
    Publication date: July 29, 2004
    Inventors: Igor Arsovski, Ali Sheikholeslami