Abstract: Methods and structures for configuring an integrated circuit including repeated cells that are divided into banks having a respective power assist and a respective operational assist are provided. A method includes configuring the banks without power assist and operational assist. The method further includes selecting the power assist for a bank based on a determination that a weak cell remains in the bank after configuring the bank with the respective operational assist.

Abstract: An integrated circuit structure comprises a static random access memory (SRAM) structure and a logic circuit. A power supply is operatively connected to the SRAM structure, and provides a first voltage to the SRAM structure. A voltage limiter is operatively connected to the power supply. The voltage limiter comprises a switching device operatively connected to the power supply. The switching device receives the first voltage and a second voltage supplied to structures external to the SRAM structure. A resistive element is operatively connected to the switching device. The switching device connects the resistive element to the power supply. The resistive element is selected to enable an output from the switching device to the logic circuit when a difference between the first voltage and the second voltage is greater than a voltage threshold value of the switching device.

Abstract: A method and device for measuring integrated circuit power supply noise and calibration of power supply noise analysis models. The method includes collecting power supply noise monitor data from an integrated circuit having one or more power supply noise monitors connected between a power supply and respective scan cells of a scan chain and one or more functional circuits connected to the scan chain by scanning a power supply noise generation pattern into the scan chain and scanning a resultant pattern out of the scan chain; converting the resultant data into actual values of selected power supply parameters; generating simulated values of the selected power supply parameters using a power supply noise simulation model based on design data of the integrated chip; comparing the actual values of the selected power supply parameters to the simulated values of the selected power supply parameters; and modifying the power supply noise simulation model based on the comparing.

Abstract: A dual word-line level shifter circuit and associated SRAM. A circuit is disclosed that includes a first transistor gated by a data input at the lower voltage, and a second transistor gated by a restore input at the higher voltage, wherein the first and second transistors are coupled along a series path to a source at the higher voltage; a control node along the series path; an output node coupled to the control node via a first pair of parallel transistors; and a feedback circuit having a second pair of parallel transistors and a feedback transistor, wherein the feedback transistor couples the second pair of parallel transistors to the control node and is gated by the output node.

Abstract: A static random access memory (SRAM) write assist circuit with leakage suppression and level control is described. In one embodiment, the SRAM write assist circuit increases the amount of boost provided in a write cycle, while in another embodiment, the SRAM write assist circuit limits the amount of boost provided at higher supply voltages.

Abstract: A differential system producing differential signals with offset cancellation utilizing a double differential input pair system is disclosed. It uses two parallel differential transistor pairs which are intentionally skewed. Nominally, the differential pairs are skewed in opposite direction from each, but with equal magnitude, so that the combination of the two differential pairs is nominally balanced. The current through each differential pair is then increased or decreased until any offset is sufficiently cancelled, using a selection means for providing an equi-potential value to first and second differential inputs in a calibration mode of the system and a comparison means for comparing first and second differential outputs in a calibration mode to determine the offset of the system.

Abstract: An SRAM delay circuit that tracks bitcell characteristics. A circuit is disclosed that includes an input node for receiving an input signal; a reference node for capturing a reference current from a plurality of reference cells; a capacitance network having a discharge that is controlled by the reference current; and an output circuit that outputs the input signal with a delay, wherein the delay is controlled by the discharge of the capacitance network.

Abstract: A content addressable memory (CAM) device includes an array of memory cells arranged in rows and columns; compare circuitry configured to indicate match results of search data presented to each row of the array; and compare circuitry configured to indicate match results of search data presented to each column of the array, thereby resulting in a two-dimensional search capability of the array.

Abstract: An integrated circuit that includes memory containing wordlines and bitcells having SRAM storage elements and being connected to the wordlines. Wordline up-level assist circuitry is provided that is designed and configured to provide a plurality of selectable voltage values that can be selected to provide the wordline up-level voltage that is provided to the bitcells during a memory read cycle and/or write cycle. In one example, the voltage value selected is selected based on characterization of the as-fabricated bitcells so as to decrease the likelihood of the bitcells experiencing a stability failure.

Abstract: A dual word-line level shifter circuit and associated SRAM. A circuit is disclosed that includes a first transistor gated by a data input at the lower voltage, and a second transistor gated by a restore input at the higher voltage, wherein the first and second transistors are coupled along a series path to a source at the higher voltage; a control node along the series path; an output node coupled to the control node via a first pair of parallel transistors; and a feedback circuit having a second pair of parallel transistors and a feedback transistor, wherein the feedback transistor couples the second pair of parallel transistors to the control node and is gated by the output node.

Abstract: Disclosed is a semiconductor chip with a digital integrated circuit, such as a memory device (e.g., static random access memory (SRAM) arrays, dynamic random access memory (DRAM) arrays, content addressable memory (CAM) arrays, etc), that can be selectively operated in either a functional mode or in a performance screening mode. In the functional mode, a first signal supplied by an external signal generator is used to activate a first device in the circuit and, in response, a second device in the circuit outputs a data output signal. In the performance screening mode, a second signal is internally generated by an internal signal generator based on the data output signal. This second signal is then used to activate the first device in the circuit and, in response, the second device outputs the data output signal.

Abstract: A static random access memory (SRAM) write assist circuit with leakage suppression and level control is described. In one embodiment, the SRAM write assist circuit increases the amount of boost provided in a write cycle, while in another embodiment, the SRAM write assist circuit limits the amount of boost provided at higher supply voltages.

Abstract: A dual word-line level shifter circuit and associated SRAM. A circuit is disclosed that includes a first transistor gated by a data input at the lower voltage, and a second transistor gated by a restore input at the higher voltage, wherein the first and second transistors are coupled along a series path to a source at the higher voltage; a control node along the series path; an output node coupled to the control node via a first pair of parallel transistors; and a feedback circuit having a second pair of parallel transistors and a feedback transistor, wherein the feedback transistor couples the second pair of parallel transistors to the control node and is gated by the output node.

Abstract: An integrated circuit that includes memory containing wordlines and bitcells having SRAM storage elements and being connected to the wordlines. Wordline up-level assist circuitry is provided that is designed and configured to provide a plurality of selectable voltage values that can be selected to provide the wordline up-level voltage that is provided to the bitcells during a memory read cycle and/or write cycle. In one example, the voltage value selected is selected based on characterization of the as-fabricated bitcells so as to decrease the likelihood of the bitcells experiencing a stability failure.

Abstract: Methods of setting wordline up-level voltage in as-fabricated SRAM. In one example, the method includes determining the relative speed, or strength, of 1) the combination of the pass-gate and pull-down devices and 2) the pull-up devices in the bitcells of the SRAM. These relative strengths are then used to adjust the wordline up-level voltage, if needed, to decrease the likelihood of the SRAM experiencing a stability failure. Corresponding systems are provided for determining the relative strengths of the devices of interest, for determining the amount of up-level voltage adjustment needed, and for selecting and setting the up-level voltage.

Abstract: A method for producing a configurable content-addressable memory (CAM) cell design, in which the method includes: inputting the configurable CAM cell design to a computer, the configurable CAM cell design capable of being configured as one of a binary CAM design and a ternary CAM design, depending on connections of a metal overlay; selecting one of a first metal overlay design for the binary CAM design and a second metal overlay design for a ternary CAM design; if the first metal overlay design is selected, then combining the first metal overlay design with the configurable CAM cell design to produce a binary CAM design including two binary CAM cells with a single search port, and outputting the binary CAM design; and if the second metal overlay design is selected, then combining the second metal overly design with the configurable CAM cell design to produce a ternary CAM design including a single ternary CAM cell with two search ports, and outputting the ternary CAM design by the computer.

Abstract: A method and device for measuring integrated circuit power supply noise and calibration of power supply noise analysis models. The method includes collecting power supply noise monitor data from an integrated circuit having one or more power supply noise monitors connected between a power supply and respective scan cells of a scan chain and one or more functional circuits connected to the scan chain by scanning a power supply noise generation pattern into the scan chain and scanning a resultant pattern out of the scan chain; converting the resultant data into actual values of selected power supply parameters; generating simulated values of the selected power supply parameters using a power supply noise simulation model based on design data of the integrated chip; comparing the actual values of the selected power supply parameters to the simulated values of the selected power supply parameters; and modifying the power supply noise simulation model based on the comparing.

Abstract: A design structure embodied in a machine readable medium used in a design process includes computational memory device having an array of memory cells arranged in rows and columns, and a pair of read word lines associated with each row of the array. The array is configured to implement, for a given cycle, either a read operation of data contained in a single selected row, or one of a plurality of different bit wise logical operations on data contained in multiple selected rows.

Abstract: A proactive noise suppression system and method for a power supply network of an integrated circuit. The system and method include receiving an IC event sequence to a memory element, correlating the IC event sequence to a storage location in a second memory element, the storage location including an anti-noise response signature, and utilizing the anti-noise response signature to proactively generate an anti-noise response in a power supply network in at least a portion of the integrated circuit at about the time of execution of the first IC event sequence. Anti-noise response signatures may be adaptively updated and/or created based on noise measurements made corresponding to execution of an IC event sequence by the integrated circuit.

Abstract: Method and systems of powering on an integrated circuit (IC) are disclosed. In one embodiment, the system includes a region in the IC including functional logic, a temperature sensor for sensing a temperature in the region when the IC is powered up and a heating element therefor; a processing unit including: a comparator for comparing the temperature against a predetermined temperature value, a controller, which in the case that the temperature is below the predetermined temperature value, delays functional operation of the IC and controls heating of the region of the IC, and a monitor for monitoring the temperature in the region; and wherein the controller, in the case that the temperature rises above the predetermined temperature value, ceases the heating and initiates functional operation of the IC.