Patents by Inventor Igor G. Kouznetsov
Igor G. Kouznetsov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10644021Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.Type: GrantFiled: May 4, 2018Date of Patent: May 5, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Thomas H. Lee, Igor G. Kouznetsov
-
Publication number: 20200066352Abstract: A method of erasing, during an erase operation, a non-volatile memory (NVM) cell of a memory device is disclosed. The erasing includes applying a first HV signal (VPOS) to a common source line (CSL). The CSL is shared among NVM cells of a sector of NVM cells. The first HV signal is above a highest voltage of a power supply. The erasing also includes applying the first HV signal to a local bit line (BL).Type: ApplicationFiled: August 5, 2019Publication date: February 27, 2020Inventors: Bogdan I. Georgescu, Gary P. Mosculak, Vijay Raghavan, Igor G. Kouznetsov
-
Publication number: 20190355583Abstract: A device including both drain extended metal-on-semiconductor (DE_MOS) and low-voltage metal-on-semiconductor (LV_MOS) transistors and methods of manufacturing the same are provided. In one embodiment, the method includes implanting ions of a first-type at a first energy level in a drain portion of a first DE_MOS transistor in a DE_MOS region of a substrate to form the first DE_MOS transistor, and implanting ions of the first-type at a second energy level in a LV_MOS region of the substrate adjust a voltage threshold of a first LV_MOS transistor, while concurrently implanting ions of the first-type at the second energy level in the drain portion of the first DE_MOS transistor to form a drain extension of the first DE_MOS transistor. Other embodiments are also provided.Type: ApplicationFiled: February 14, 2019Publication date: November 21, 2019Inventors: Sungkwon Lee, Igor G. Kouznetsov, Gyu-Chul Kim
-
Publication number: 20190318785Abstract: A method for operating a memory device includes the steps of providing a first voltage to a first transistor of a first memory cell and a third transistor of a second memory cell, providing a second voltage to a gate of a second transistor of the first memory cell and a gate of a fourth transistor of the second memory cell, and providing a third voltage to a gate of the first transistor of the first memory cell and a gate of the third transistor of the second memory cell. Other embodiments are also described.Type: ApplicationFiled: January 10, 2019Publication date: October 17, 2019Inventors: Xiaojun Yu, Venkatraman Prabhakar, Igor G. Kouznetsov, Long T. Hinh, Bo Jin
-
Patent number: 10373688Abstract: A method of erasing, during an erase operation, a non-volatile memory (NVM) cell of a memory device is disclosed. The erasing includes applying a first HV signal (VPOS) to a common source line (CSL). The CSL is shared among NVM cells of a sector of NVM cells. The first HV signal is above a highest voltage of a power supply. The erasing also includes applying the first HV signal to a local bit line (BL).Type: GrantFiled: June 27, 2017Date of Patent: August 6, 2019Assignee: LONGITUDE FLASH MEMORY SOLUTIONS LTD.Inventors: Bogdan I. Georgescu, Gary P. Moscaluk, Vijay Raghavan, Igor G. Kouznetsov
-
Patent number: 10262747Abstract: A non-volatile memory that includes a shared source line configuration and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array.Type: GrantFiled: November 8, 2017Date of Patent: April 16, 2019Assignee: Cypress Semiconductor CorporationInventors: Ryan T. Hirose, Igor G. Kouznetsov, Venkatraman Prabhakar, Kaveh Shakeri, Bogdan Georgescu
-
Patent number: 10217639Abstract: A device including both drain extended metal-on-semiconductor (DE_MOS) and low-voltage metal-on-semiconductor (LV_MOS) transistors and methods of manufacturing the same are provided. In one embodiment, the method includes implanting ions of a first-type at a first energy level in a drain portion of a first DE_MOS transistor in a DE_MOS region of a substrate to form the first DE_MOS transistor, and implanting ions of the first-type at a second energy level in a LV_MOS region of the substrate adjust a voltage threshold of a first LV_MOS transistor, while concurrently implanting ions of the first-type at the second energy level in the drain portion of the first DE_MOS transistor to form a drain extension of the first DE_MOS transistor. Other embodiments are also provided.Type: GrantFiled: September 1, 2015Date of Patent: February 26, 2019Assignee: Cypress Semiconductor CorporationInventors: Sungkwon Lee, Igor G. Kouznetsov, Gyu-Chul Kim
-
Patent number: 10204691Abstract: A non-volatile memory that includes a shared source line configuration and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array.Type: GrantFiled: November 8, 2017Date of Patent: February 12, 2019Assignee: Cypress Semiconductor CorporationInventors: Ryan T. Hirose, Igor G. Kouznetsov, Venkatraman Prabhakar, Kaveh Shakeri, Bogdan Georgescu
-
Publication number: 20180254286Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.Type: ApplicationFiled: May 4, 2018Publication date: September 6, 2018Inventors: Thomas H. Lee, Igor G. Kouznetsov
-
Patent number: 10032517Abstract: A system including a memory architecture is described. In one embodiment, the memory architecture includes an array of non-volatile memory cells, a first independently controlled voltage generation circuit, a plurality of register bits to store programmable values used by the independently controlled voltage generation circuit and a control circuit coupled to the first independently controlled voltage generation circuit. The first independently controlled voltage generation circuit is coupled to supply a positive voltage to the array during program and erase operations so that a magnitude of the positive voltage is applied across a storage note of an accessed memory cell of the array. The plurality of register bits to store programmable values used by the independently controlled voltage generation circuit to control the magnitude of the positive voltage. The control circuit controls a duration of the positive voltage. Other embodiments are also described.Type: GrantFiled: April 15, 2015Date of Patent: July 24, 2018Assignee: Cypress Semiconductor CorporationInventors: Ryan Tasuo Hirose, Fredrick B. Jenne, Vijay Raghavan, Igor G. Kouznetsov, Paul Fredrick Ruths, Cristinel Zonte, Bogdan I. Georgescu, Leonard Vasile Gitlan, James Paul Myers
-
Publication number: 20180166140Abstract: A system including a memory architecture is described. In one embodiment, the memory architecture includes an array of non-volatile memory cells, a first independently controlled voltage generation circuit, a plurality of register bits to store programmable values used by the independently controlled voltage generation circuit and a control circuit coupled to the first independently controlled voltage generation circuit. The first independently controlled voltage generation circuit is coupled to supply a positive voltage to the array during program and erase operations so that a magnitude of the positive voltage is applied across a storage note of an accessed memory cell of the array. The plurality of register bits to store programmable values used by the independently controlled voltage generation circuit to control the magnitude of the positive voltage. The control circuit controls a duration of the positive voltage. Other embodiments are also described.Type: ApplicationFiled: April 15, 2015Publication date: June 14, 2018Inventors: Ryan Tasuo Hirose, Fredrick B. Jenne, Vijay Raghavan, Igor G. Kouznetsov, Paul Fredrick Ruths, Cristinel Zonte, Bogdan I. Georgescu, Leonard Vasile Gitlan, James Paul Myers
-
Patent number: 9922988Abstract: Memory devices and methods for forming the same are disclosed. In one embodiment, the device includes a non-volatile memory (NVM) transistor formed in a first region of a substrate, the NVM transistor comprising a channel and a gate stack on the substrate overlying the channel. The gate stack includes a dielectric layer on the substrate, a charge-trapping layer on the dielectric layer, an oxide layer overlying the charge-trapping layer, a first gate overlying the oxide layer, and a first silicide region overlying the first gate. The device includes a metal-oxide-semiconductor transistor formed in a second region of the substrate comprising a gate oxide overlying the substrate in the second region, a second gate overlying the gate oxide, and second silicide region overlying the second gate. A strain inducing structure overlies at least the NVM transistor and a surface of the substrate in the first region of the substrate.Type: GrantFiled: March 6, 2017Date of Patent: March 20, 2018Assignee: Cypress Semiconductor CorporationInventors: Krishnaswamy Ramkumar, Igor G. Kouznetsov, Venkatraman Prabhakar
-
Publication number: 20180068735Abstract: A non-volatile memory that includes a shared source line configuration and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array.Type: ApplicationFiled: November 8, 2017Publication date: March 8, 2018Applicant: Cypress Semiconductor CorporationInventors: Ryan T. Hirose, Igor G. Kouznetsov, Venkatraman Prabhakar, Kaveh Shakeri, Bogdan Georgescu
-
Patent number: 9899089Abstract: A system including a memory architecture is described. In one embodiment, the memory architecture includes an array of non-volatile memory cells, a first independently controlled voltage generation circuit, a plurality of register bits to store programmable values used by the independently controlled voltage generation circuit and a control circuit coupled to the first independently controlled voltage generation circuit. The first independently controlled voltage generation circuit is coupled to supply a positive voltage to the array during program and erase operations so that a magnitude of the positive voltage is applied across a storage node of an accessed memory cell of the array. The plurality of register bits to store programmable values used by the independently controlled voltage generation circuit to control the magnitude of the positive voltage. The control circuit controls a duration of the positive voltage. Other embodiments are also described.Type: GrantFiled: September 24, 2013Date of Patent: February 20, 2018Assignee: Cypress Semiconductor CorporationInventors: Ryan Tasuo Hirose, Fredrick B. Jenne, Vijay Raghavan, Igor G. Kouznetsov, Paul Fredrick Ruths, Cristinel Zonte, Bogdan I. Georgescu, Leonard Vasile Gitlan, James Paul Myers
-
Publication number: 20170365346Abstract: A method of erasing, during an erase operation, a non-volatile memory (NVM) cell of a memory device is disclosed. The erasing includes applying a first HV signal (VPOS) to a common source line (CSL). The CSL is shared among NVM cells of a sector of NVM cells. The first HV signal is above a highest voltage of a power supply. The erasing also includes applying the first HV signal to a local bit line (BL).Type: ApplicationFiled: June 27, 2017Publication date: December 21, 2017Applicant: Cypress Semiconductor CorporationInventors: Bogdan I. Georgescu, Gary P. Moscaluk, Vijay Raghavan, Igor G. Kouznetsov
-
Patent number: 9847137Abstract: A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array to reduce a bias applied to a non-volatile memory transistor in an unselected memory cell to reduce program disturb of data programmed in the unselected memory cell due to programming.Type: GrantFiled: August 30, 2016Date of Patent: December 19, 2017Assignee: Cypress Semiconductor CorporationInventors: Ryan T. Hirose, Igor G. Kouznetsov, Venkatraman Prabhakar, Kaveh Shakeri, Bogdan Georgescu
-
Patent number: 9818484Abstract: Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to a common source line. The methods include receiving a third voltage at a gate of the second transistor and a gate of the fourth transistor that may cause them to operate in cutoff mode. The methods may include receiving a fourth voltage at a gate of the first transistor. The fourth voltage may cause a change in a charge storage layer included in the first transistor.Type: GrantFiled: March 22, 2017Date of Patent: November 14, 2017Assignee: Cypress Semiconductor CorporationInventors: Xiaojun Yu, Venkatraman Prabhakar, Igor G. Kouznetsov, Long T Hinh, Bo Jin
-
Publication number: 20170278573Abstract: Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to a common source line. The methods include receiving a third voltage at a gate of the second transistor and a gate of the fourth transistor that may cause them to operate in cutoff mode. The methods may include receiving a fourth voltage at a gate of the first transistor. The fourth voltage may cause a change in a charge storage layer included in the first transistor.Type: ApplicationFiled: March 22, 2017Publication date: September 28, 2017Applicant: Cypress Semiconductor CorporationInventors: Xiaojun Yu, Venkatraman Prabhakar, Igor G. Kouznetsov, Long T. Hinh, Bo Jin
-
Publication number: 20170263622Abstract: Memory devices and methods for forming the same are disclosed. In one embodiment, the device includes a non-volatile memory (NVM) transistor formed in a first region of a substrate, the NVM transistor comprising a channel and a gate stack on the substrate overlying the channel. The gate stack includes a dielectric layer on the substrate, a charge-trapping layer on the dielectric layer, an oxide layer overlying the charge-trapping layer, a first gate overlying the oxide layer, and a first silicide region overlying the first gate. The device includes a metal-oxide-semiconductor transistor formed in a second region of the substrate comprising a gate oxide overlying the substrate in the second region, a second gate overlying the gate oxide, and second silicide region overlying the second gate. A strain inducing structure overlies at least the NVM transistor and a surface of the substrate in the first region of the substrate.Type: ApplicationFiled: March 6, 2017Publication date: September 14, 2017Applicant: Cypress Semiconductor CorporationInventors: Krishnaswamy Ramkumar, Igor G. Kouznetsov, Venkatraman Prabhakar
-
Patent number: 9704585Abstract: A method of erasing, during an erase operation, a non-volatile memory (NVM) cell of a memory device is disclosed. The erasing includes applying a first HV signal (VPOS) to a common source line (CSL). The CSL is shared among NVM cells of a sector of NVM cells. The first HV signal is above a highest voltage of a power supply. The erasing also includes applying the first HV signal to a local bit line (BL).Type: GrantFiled: September 18, 2015Date of Patent: July 11, 2017Assignee: Cypress Semiconductor CorporationInventors: Bogdan I. Georgescu, Gary P. Mosculak, Vijay Raghavan, Igor G. Kouznetsov