METHOD OF FORMING DRAIN EXTENDED MOS TRANSISTORS FOR HIGH VOLTAGE CIRCUITS
A device including both drain extended metal-on-semiconductor (DE_MOS) and low-voltage metal-on-semiconductor (LV_MOS) transistors and methods of manufacturing the same are provided. In one embodiment, the method includes implanting ions of a first-type at a first energy level in a drain portion of a first DE_MOS transistor in a DE_MOS region of a substrate to form the first DE_MOS transistor, and implanting ions of the first-type at a second energy level in a LV_MOS region of the substrate adjust a voltage threshold of a first LV_MOS transistor, while concurrently implanting ions of the first-type at the second energy level in the drain portion of the first DE_MOS transistor to form a drain extension of the first DE_MOS transistor. Other embodiments are also provided.
This application is a continuation of U.S. patent application Ser. No. 14/842,326 filed on Sep. 1, 2015, which is a continuation of U.S. patent application Ser. No. 14/108,967 filed on Dec. 17, 2013, now U.S. Pat. No. 9,123,642, issued Sep. 1, 2015, which claims priority under 35 U.S.C. 119(e) to U.S. Provisional Patent Application Ser. No. 61/857,151, filed Jul. 22, 2013, all of which are hereby incorporated by reference herein in their entirety.
TECHNICAL FIELDThis disclosure relates generally to fabrication of semiconductor devices, and more particularly to drain extended metal-on-semiconductor (DE_MOS) transistors used in high-voltage (HV) circuits of devices such as Non-Volatile Memories (NVM) and methods for fabricating the same.
BACKGROUNDWhile many types of integrated circuits may be designed to operate with a single internal voltage, it is often desirable to provide an integrated circuit (IC) including devices (e.g., transistors as well as passive circuit elements) that operate at two or more different voltage levels. Examples of such ICs include a Non-Volatile Memories (NVM) and an IC including a NVM or a flash macro, such as a micro-controller, microprocessor or programmable system on a chip (PSOC). Such a circuit typically includes low-voltage metal-on-semiconductor (LV_MOS) transistors used in logic and/or switching applications and designed to operate at a voltage of less than from about 2.5 to about 3.3 volts (V), and other high-voltage metal-on-semiconductor (HV_MOS) transistors used in NVM applications such as in input/output (I/O) cells or drivers, and typically designed to operate at voltages of about 9V or greater.
A conventional approach to integrating a HV_MOS transistor into such circuit, illustrated in
Another approach to integrating a HV_MOS transistor into such circuit, illustrated in
The above solutions, while an improvement over previous approaches to integrating HV and LV devices in the same circuit are not wholly satisfactory for a number of reasons including the fact that they significantly increase the number of process steps and/or device footprint. In particular, both of the above approaches require a thicker gate oxide, which it typically takes 3-5 additional mask layers to introduce in to an existing MOS process flow. These additional mask layers significantly increase production costs and time while decreasing a yield of working circuits. Moreover, the introduction of these additional mask layers is not compatible with logic/mixed mode process technologies at foundries producing 130 nm technology nodes and below, which typically require a low thermal budget and limited number of wet processing steps. Finally, with regard to the RESURF-type DE_MOS transistor 200 it is noted the inclusion of the STI 214 within the RESURF-type drain extension 210 greatly increases the footprint of the device, making this approach unsuitable for applications in which the HV_MOS is part of circuit having tight critical dimension to space (CD/space) design rules, i.e., 0.47/1.2 μm or less, making it very difficult to use these devices in pitched circuits such as an I/O cells or drivers of a NVM.
SUMMARYIn light of the above, it would be desirable to manufacture integrated circuits including drain extended metal-on-semiconductor (DE_MOS), high-voltage metal-on-semiconductor (HV_MOS) and low-voltage metal-on-semiconductor (LV_MOS) transistors compatible with logic/mixed mode CMOS process technologies. It would also be desirable to arrive at some way of forming DE_MOS and HV_MOS transistors that do not suffer from the drawbacks of the conventional approaches described above.
According to one embodiment of the present disclosure, the method includes implanting in a drain portion of a first DE_MOS transistor in a DE_MOS region of a substrate ions of a first-type at a first energy level to form the first DE_MOS transistor, and implanting in a LV_MOS region of the substrate ions of the first-type at a second energy level adjust a voltage threshold of a first LV_MOS transistor, while concurrently implanting in the drain portion of the first DE_MOS transistor ions of the first-type at the second energy level to form a drain extension of the first DE_MOS transistor.
In another embodiment, the method further includes forming a mask over the substrate exposing a part of the drain portion of the first DE_MOS transistor, and implanting ions of the first-type at a third energy level to form a graduated drain extension of the first DE_MOS transistor.
The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.
Various embodiments of the present invention will now be described with reference to a number of diagrams. The embodiments include methods of concurrently forming a high-voltage drain-extended metal-on-semiconductor (DE_MOS) transistor, as well as a low-voltage metal-on-semiconductor (LV_MOS) and high-voltage metal-on-semiconductor (HV_MOS) transistors in a number of different circuits and applications. In particular embodiments, the DE_MOS transistor may be formed in the same substrate as a LV_MOS transistor in an input/output (I/O) cell in a non-volatile memory (NVM), or in a driver for the NVM.
In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be evident, however, to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known structures, and techniques are not shown in detail or are shown in block diagram form in order to avoid unnecessarily obscuring an understanding of this description.
Reference in the description to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification do not necessarily all refer to the same embodiment. The term to couple as used herein may include both to directly electrically connect two or more components or elements and to indirectly connect through one or more intervening components.
The terms “over,” “under,” “between,” and “on” as used herein refer to a relative position of one layer with respect to other layers. As such, for example, one layer deposited or disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer deposited or disposed between layers may be directly in contact with the layers or may have one or more intervening layers. In contrast, a first layer “on” a second layer is in contact with that second layer. Additionally, the relative position of one layer with respect to other layers is provided assuming operations deposit, modify and remove films relative to a starting substrate without consideration of the absolute orientation of the substrate.
Embodiments of a high-voltage drain-extended metal-on-semiconductor (DE_MOS) transistor according to the present disclosure will now be described with reference to
Referring to
In one very particular example, a suitable VTP implant may include low energy ions implanted at a dose in the range of 1012 to 1014 ions/cm2. Implant energies may be in the range of about 40-60 keV. A suitable VTPIO implant may include high energy ions implanted at a dose in the range of 1012 to 1013 ions/cm2, at implant energies in the range of about 60-150 keV. Implanted ions to form the N-drain extension 318 of a DE_MOS may include the Arsenic or Phosphorus species.
Referring to
Finally,
In a second embodiment shown in
In accordance with the present disclosure the DE_MOS transistor 320 further includes a P-drain extension 334 separating the channel 328 from the P+ doped drain 326. Generally, the P-drain extension 334 comprises an implant or dopant concentration that is lighter than that of the P+ doped drain 326. In some embodiments, such as that shown, the P-drain extension 334 has implant or dopant concentration substantially equal to at least a sum of a voltage threshold adjust implant (VTN) of a second LV_MOS transistor (not shown in this figure) formed concurrently elsewhere on the same substrate, and voltage threshold adjust implant (VTNIO) of a non-drain extended, second HV_MOS transistor (not shown in this figure) such as I/O transistor, formed concurrently elsewhere on the same substrate. It will be understood that the second LV_MOS transistor and second HV_MOS transistor are of the opposite type of both the P-type DE_MOS or (DE_PMOS) and the first LV_MOS transistor and first HV_MOS transistor described above with respect to
In one very particular example, a suitable VTN implant may include low energy ions implanted at a dose in the range of 1012 to 1014 ions/cm2. Implant energies may be in the range of about 20-30 keV. A suitable VTNIO implant may include high energy ions may be implanted at a dose in the range of 1012 to 1013 ions/cm2, at implant energies in the range of about 30-70 keV. Implanted ions to form the P-drain extension 334 of a DE_PMOS may include the BF2 or Boron11 species.
An embodiment of a process or method for manufacturing an IC including an LV_MOS transistor, HV_MOS transistor and a DE_MOS transistor according to an embodiment of the present disclosure will now be described in detail with reference to
To simplify understanding of the method for manufacturing an IC including an LV_MOS transistor, HV_MOS transistor and an DE_MOS transistor, the surface of a substrate 502 is divided into three different regions including a DE_MOS region 506 in which one or more DE_MOS transistors will be formed, a LV_MOS region 508 in which one or more LV_MOS transistors will be formed and a HV_MOS region 510 in which one or more HV_MOS transistors will be formed. In the embodiment shown, each of the DE_MOS region 506, the LV_MOS region 508 and the HV_MOS region 510 include one P-well and one N-well in which different types of MOS transistors, either PMOS or NMOS will be formed.
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
Gate layer 544 generally includes poly-silicon, titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), aluminum, copper or alloys or mixtures thereof, and is deposited by physical vapor deposition, such as sputtering, evaporation, or electroless plating to a thickness of from about 500 to about 3000 Å. The gate layer 544 and gate oxides 540, 542 are then patterned to form the gate stacks illustrated in
The sources 546 and drains 548 can be formed by ion implantation to complete all DE_MOS, LV_MOS and HV_MOS transistors.
It will be understood by those skilled in the art that the embodiment of a process or method of manufacturing or fabricating an IC including DE_MOS, LV_MOS and HV_MOS transistors described above advantageously minimizes changes to the standard complimentary metal-oxide-semiconductor (CMOS) process flow, including just modifications of existing LV and HV threshold voltage adjust masks to form a DE_MOS transistor in a mixed mode circuit. By eliminating the need for additional mask layers typically required with thicker oxides production costs and time are significantly decreased while a yield of working circuits increased. It will further be understood that the DE_MOS transistor fabricated by the disclosed method minimizes the footprint of the device, making this approach particular well suited for applications in which the DE_MOS transistor is part of circuit having tight critical dimension to space (CD/space) design rules, i.e., 0.47/1.2 um or less, making it very useful in pitched circuits such as an I/O cells or NVM array in a non-volatile macro circuit.
Embodiments of a DE_MOS transistor including a graduated drain extension and methods of forming the same according to the present disclosure will now be described with reference to
In an alternative embodiment, the method further includes forming a DE_MOS transistor having a graduated drain extension to improve “on”-state resistance and/or safe operating area of the DE_MOS transistor.
Referring to
In accordance with the present embodiment the DE_MOS transistor 1002 further includes an additional implant 1020 in the N-drain extension 1018. The addition of this additional implant 1020 to the drain extension to improve the “on” resistance and/or expand safe operating area (SOA) of the DE_MOS transistor.
Referring to
As indicated by horizontal arrows in
In a second embodiment shown in
In accordance with the present disclosure the DE_MOS transistor 1022 further includes, in addition to a P-drain extension 1036 separating the channel 1030 from the P+ doped drain 1028, an additional implant 1038 in the P-drain extension 1036 to improve the “on” resistance and/or expand safe operating area (SOA) of the DE_MOS transistor.
Referring to
Thus, embodiments of mixed mode integrated circuits and in particular of non-volatile memories including both DE_MOS and LV_MOS transistors and methods of manufacturing the same have been described. Although the present disclosure has been described with reference to specific exemplary embodiments, it will be evident that various modifications and changes may be made to these embodiments without departing from the broader spirit and scope of the disclosure. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.
The Abstract of the Disclosure is provided to comply with 37 C.F.R. § 1.72(b), requiring an abstract that will allow the reader to quickly ascertain the nature of one or more embodiments of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.
Reference in the description to one embodiment or an embodiment means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the circuit or method. The appearances of the phrase one embodiment in various places in the specification do not necessarily all refer to the same embodiment.
Claims
1. A method comprising:
- implanting ions of a first-type at a first energy level in a drain portion of a drain extended metal-on-semiconductor (DE_MOS) transistor in a DE_MOS region of a substrate to form a first DE_MOS transistor; and
- implanting ions of the first-type at a second energy level in a low-voltage metal-on-semiconductor (LV_MOS) region of the substrate to adjust a voltage threshold of a first LV_MOS transistor, while concurrently implanting ions of the first-type at the second energy level in the drain portion of the first DE_MOS transistor to form a drain extension of the first DE_MOS transistor.
2. The method of claim 1 wherein implanting ions of the first-type at the first energy level in the drain portion of the first DE_MOS transistor, comprises concurrently implanting ions of the first-type at the first energy level in a high-voltage metal-on-semiconductor (HV_MOS) region of the substrate to adjust a voltage threshold of a first high-voltage metal-on-semiconductor (HV_MOS) transistor in the HV_MOS region.
3. The method of claim 2 further comprising implanting ions of a second-type at the first energy level in a drain portion of a second DE_MOS transistor in the DE_MOS region while concurrently implanting ions of the second-type at the first energy level in the HV_MOS region of the substrate to adjust a voltage threshold of a second HV_MOS transistor in the HV_MOS region.
4. The method of claim 3 further comprising implanting ions of the second-type at the second energy level in the LV_MOS region of the substrate to adjust a voltage threshold of a second LV_MOS transistor, while concurrently implanting ions of the second-type at the second energy level in the drain portion of the second DE_MOS transistor to form a drain extension of the second DE_MOS transistor.
5. The method of claim 4 wherein:
- implanting ions of the second-type at the first energy level in the HV_MOS region of the substrate to adjust a voltage threshold of the second HV_MOS transistor, further comprises concurrently implanting ions of the second-type at the first energy level in the DE_MOS region to form a source portion of the first DE_MOS transistor; and
- implanting ions of the first-type at the first energy level in the HV_MOS region of the substrate to adjust a voltage threshold of the first HV_MOS transistor, further comprises concurrently implanting ions of the first-type at the first energy level in the DE_MOS region to form a source portion of the second DE_MOS transistor.
6. The method of claim 5 wherein the second energy level is lower than the first energy level.
7. The method of claim 5 further comprising forming sources and drains in the first DE_MOS transistor and the second DE_MOS transistor, the first LV_MOS transistor and the second LV_MOS transistor, and the first HV_MOS transistor and the second HV_MOS transistor.
8. The method of claim 1 wherein the DE_MOS formed is in an input/output (I/O) cell of a non-volatile memory (NVM).
9. The method of claim 1 wherein the DE_MOS formed is on pitch with a non-volatile memory (NVM) array of a NVM.
10. The method of claim 1 further comprising forming a mask over the substrate exposing a part of the drain portion of the first DE_MOS transistor, and implanting ions of the first-type at a third energy level to form a graduated drain extension of the first DE_MOS transistor.
11. A method comprising:
- forming a first threshold voltage adjust mask over a surface of a substrate to expose a high-voltage metal-on-semiconductor (HV_MOS) transistor in a high-voltage metal-on-semiconductor (HV_MOS) region of the substrate, and to expose a drain portion of a drain extended metal-on-semiconductor (DE_MOS) transistor in a DE_MOS region of the substrate;
- implanting ions of a first-type at a first energy level in the drain portion of the DE_MOS transistor, while concurrently implanting ions of the first-type at the first energy level in the HV_MOS transistor to adjust a voltage threshold of the HV_MOS;
- forming a second threshold voltage adjust mask over the surface of a substrate to expose a low-voltage metal-on-semiconductor (LV_MOS) transistor in a low-voltage metal-on-semiconductor (LV_MOS) region of the substrate, and to expose the drain portion of the DE_MOS transistor; and
- implanting ions of the first-type at a second energy level in the drain portion of the DE_MOS transistor, while concurrently implanting ions of the first-type at the second energy level in the LV_MOS transistor to adjust a voltage threshold of the LV_MOS.
12. The method of claim 11 wherein the second energy level is lower than the first energy level.
13. The method of claim 11 further comprising forming sources and drains in the DE_MOS transistor the LV_MOS transistor, and HV_MOS transistor.
14. The method of claim 11 wherein the DE_MOS formed is in an input/output (I/O) cell of a non-volatile memory (NVM).
15. The method of claim 11 wherein the DE_MOS formed is on pitch with a non-volatile memory (NVM) array of a NVM.
16. The method of claim 11 further comprising forming a mask over the substrate exposing a part of the drain portion of the DE_MOS transistor, and implanting ions of the first-type at a third energy level to form a graduated drain extension of the DE_MOS transistor.
17. A method comprising:
- implanting ions of a first-type at a first energy level in a drain portion of a drain extended metal-on-semiconductor (DE_MOS) transistor in a DE_MOS region of a substrate to form a DE_MOS transistor, while concurrently implanting ions of the first-type at the first energy level in a high-voltage metal-on-semiconductor (HV_MOS) region of the substrate to adjust a voltage threshold of a HV_MOS transistor in the HV_MOS region.
18. The method of claim 17 further comprising implanting ions of the first-type at a second energy level in a low-voltage metal-on-semiconductor (LV_MOS) region of the substrate to adjust a voltage threshold of a LV_MOS transistor, while concurrently implanting ions of the first-type at the second energy level in the drain portion of the DE_MOS transistor to form a drain extension of the DE_MOS transistor.
19. The method of claim 18 wherein the second energy level is lower than the first energy level.
20. The method of claim 18 further comprising forming a first gate oxide for the DE_MOS transistor while concurrently forming a second gate oxide for the HV_MOS transistor.
Type: Application
Filed: Feb 14, 2019
Publication Date: Nov 21, 2019
Inventors: Sungkwon Lee (Saratoga, CA), Igor G. Kouznetsov (San Francisco, CA), Gyu-Chul Kim (Lakeville, MN)
Application Number: 16/275,521