Patents by Inventor Igor Genshaft

Igor Genshaft has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260252253
    Abstract: Data relocation or rebuild can be accomplished much more efficiently by using either a metadata option or an mSet option. The metadata option involves scanning metadata in a source block to find logical block addresses (LBAs) that belong to a particular mSet. Thereafter, all of the data for any found LBAs for the particular mSet are copied to the destination block one after another. The mSet option involves bringing the mSet related to one of the LBAs found in the metadata to a specific storage location, such as random access memory (RAM), and then scanning the mSet to find any jumbo block addresses (JBAs) that belong to the source block. Thereafter, all of the data for the found JBAs are copied to the destination block one after another. Either option results in reducing the amount of mSet loading and ensures more efficient sequential reads.
    Type: Application
    Filed: February 25, 2025
    Publication date: August 27, 2026
    Applicant: Sandisk Technologies, Inc.
    Inventors: Igor GENSHAFT, Vered KELNER, Marina FRID
  • Patent number: 12711024
    Abstract: The apparatus for recovery of protected segments (mSets) at run time or after an ungraceful shutdown (UGSD) event, such as in a host memory buffer (HMB) error case, utilizes a shadow structure (e.g., shadow update layer (uLayer)) that is be stored in the memory device (e.g., flash) in an mBlock and is used only for recovery of protected mSets. The approach also allows significantly increasing a number of protected mSets because the proposed shadow uLayer structure avoids flushing all protected mSets at Control Sync (CS). The expected performance gains and reducing of write amplification of control data cover the overhead costs of processing the shadow structure.
    Type: Grant
    Filed: October 14, 2024
    Date of Patent: August 18, 2026
    Assignee: Sandisk Technologies, Inc.
    Inventors: Marina Frid, Vered Kelner, Igor Genshaft
  • Patent number: 12699520
    Abstract: The present disclosure generally relates to improved performance for jumbo blocks (JBs) with a low die count. Rather than variable performance for each irregular jumbo block (IRJB), the same performance can be achieved with all IRJBs. Using an IRJB size unification process relinking the die blocks from relatively rich (i.e., large) IRJBs with the die blocks of the poor (i.e., small) IRJBs occurs in a die table. The relink blocks are moved to IRJBs that have missing die blocks in the same die where the die blocks were taken from. In so doing, the IRJBs in the die table are of the same size.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: August 4, 2026
    Assignee: Sandisk Technologies, Inc.
    Inventors: Igor Genshaft, Vered Kelner, Marina Frid
  • Patent number: 12625632
    Abstract: When performing a consolidation process, entries (uRuns) in the update region (uRegion) of an update layer (uLayer) are typically erased immediately after the data in the uRuns is updated to a master layer (mLayer). The data may, at a later time, be copied back to the uRuns for read purposes. Rather than erasing the uRuns and then copying the data back to the uRuns for read purposes, the uRuns can simply not be erased after the consolidation. If space is needed, the uRuns can be erased without any need for consolidation. Furthermore, if another consolidation process occurs, the uRuns that were previously consolidated, but not erased, can simply be erased.
    Type: Grant
    Filed: April 8, 2024
    Date of Patent: May 12, 2026
    Assignee: Sandisk Technologies, Inc.
    Inventors: Marina Frid, Vered Kelner, Igor Genshaft
  • Publication number: 20260104969
    Abstract: The apparatus for recovery of protected segments (mSets) at run time or after an ungraceful shutdown (UGSD) event, such as in a host memory buffer (HMB) error case, utilizes a shadow structure (e.g., shadow update layer (uLayer)) that is be stored in the memory device (e.g., flash) in an mBlock and is used only for recovery of protected mSets. The approach also allows significantly increasing a number of protected mSets because the proposed shadow uLayer structure avoids flushing all protected mSets at Control Sync (CS). The expected performance gains and reducing of write amplification of control data cover the overhead costs of processing the shadow structure.
    Type: Application
    Filed: October 14, 2024
    Publication date: April 16, 2026
    Applicant: Sandisk Technologies, Inc.
    Inventors: Marina FRID, Vered KELNER, Igor GENSHAFT
  • Patent number: 12475032
    Abstract: The present disclosure generally relates to improved consolidation in dual-layer FTL. In preparation for the next control sync, the controller will generate a copy the uRegions uHeaders and will continue updating the uLayer uRegion with new uRun entries. After completing the control sync operation, the controller will then select the best consolidation candidate based on comparing the uRegion uHeaders with their copy and determining the uRegion with the maximum uRuns difference or the greatest number of uRun updates in case the uRun updates difference is less than a threshold. The controller then reads the selected mSets from the flash memory to its cache and merges the updated uRuns with the cached mSets.
    Type: Grant
    Filed: July 19, 2023
    Date of Patent: November 18, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Marina Frid, Vered Kelner, Igor Genshaft
  • Publication number: 20250315179
    Abstract: When performing a consolidation process, entries (uRuns) in the update region (uRegion) of an update layer (uLayer) are typically erased immediately after the data in the uRuns is updated to a master layer (mLayer). The data may, at a later time, be copied back to the uRuns for read purposes. Rather than erasing the uRuns and then copying the data back to the uRuns for read purposes, the uRuns can simply not be erased after the consolidation. If space is needed, the uRuns can be erased without any need for consolidation. Furthermore, if another consolidation process occurs, the uRuns that were previously consolidated, but not erased, can simply be erased.
    Type: Application
    Filed: April 8, 2024
    Publication date: October 9, 2025
    Applicant: SanDisk Technologies LLC
    Inventors: Marina FRID, Vered KELNER, Igor GENSHAFT
  • Publication number: 20240319898
    Abstract: The present disclosure generally relates to improved performance for jumbo blocks (JBs) with a low die count. Rather than variable performance for each irregular jumbo block (IRJB), the same performance can be achieved with all IRJBs. Using an IRJB size unification process relinking the die blocks from relatively rich (i.e., large) IRJBs with the die blocks of the poor (i.e., small) IRJBs occurs in a die table. The relink blocks are moved to IRJBs that have missing die blocks in the same die where the die blocks were taken from. In so doing, the IRJBs in the die table are of the same size.
    Type: Application
    Filed: July 28, 2023
    Publication date: September 26, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Igor GENSHAFT, Vered KELNER, Marina FRID
  • Publication number: 20240289268
    Abstract: The present disclosure generally relates to improved consolidation in dual-layer FTL. In preparation for the next control sync, the controller will generate a copy the uRegions uHeaders and will continue updating the uLayer uRegion with new uRun entries. After completing the control sync operation, the controller will then select the best consolidation candidate based on comparing the uRegion uHeaders with their copy and determining the uRegion with the maximum uRuns difference or the greatest number of uRun updates in case the uRun updates difference is less than a threshold. The controller then reads the selected mSets from the flash memory to its cache and merges the updated uRuns with the cached mSets.
    Type: Application
    Filed: July 19, 2023
    Publication date: August 29, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Marina FRID, Vered KELNER, Igor GENSHAFT
  • Patent number: 12039179
    Abstract: The present disclosure generally relates to improving memory management. When valid mSets are relocated via mBlock compaction, the uLayer will have some updates for the mSet and consolidation of the mSet will write the mSet to mBlock once more. The disclosure herein reduces the impact of the problem that the same more frequently updated mSets uRegions are consolidated many times and written to flash where the less updated mSets uRegions become trapped uRegions in the uLayer reducing the uLayer capacity and efficacy. The disclosure provides guidance on how to synchronize the uLayer consolidations efficiently and preventing trapping of unused uRegions in the uLayer that reduces the uLayer capacity and efficiency. The synchronizing is between the uLayer consolidation to the mLayer and the mBlock compaction process such that the smaller uLayer efficacy will not be reduced due to trapped uRegions that are less frequently updated.
    Type: Grant
    Filed: September 29, 2022
    Date of Patent: July 16, 2024
    Assignee: Sandisk Technologies, Inc.
    Inventors: Marina Frid, Igor Genshaft
  • Patent number: 12019899
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to relocate first valid data from a first source block to a destination block, relocate second valid data from a second source block to the destination block, determine that the destination block is closed, re-mark the first and second source block with a second indication, and erase the source blocks that have the second indication. The first source block and the second source block are marked with a first indication after each respective data is relocated. The first indication indicates that the source block cannot be freed. The second indication indicates that the destination block is closed and the associated source blocks can be erased. Prior to closing the destination block, parity data may be generated for the data of the destination block and programmed to the destination block.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: June 25, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Vered Kelner, Marina Frid, Igor Genshaft
  • Patent number: 11960397
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to generate a first mapping portion and a second mapping portion, where the first mapping portion and the second mapping portion correspond to a same data set, and where the first mapping portion and the second mapping portion includes one or more parity bits, receive an update for the same data set, update the first mapping portion and the second mapping portion based on the update, where the second mapping portion is updated non-concurrently to updating the first mapping portion, and where the updating includes flipping a parity bit of the one or more parity bits, and determine whether the one or more parity bits of the first mapping portion matches the one or more parity bits of the second mapping portion.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: April 16, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Vered Kelner, Marina Frid, Igor Genshaft
  • Publication number: 20240111443
    Abstract: The present disclosure generally relates to improving memory management. When valid mSets are relocated via mBlock compaction, the uLayer will have some updates for the mSet and consolidation of the mSet will write the mSet to mBlock once more. The disclosure herein reduces the impact of the problem that the same more frequently updated mSets uRegions are consolidated many times and written to flash where the less updated mSets uRegions become trapped uRegions in the uLayer reducing the uLayer capacity and efficacy. The disclosure provides guidance on how to synchronize the uLayer consolidations efficiently and preventing trapping of unused uRegions in the uLayer that reduces the uLayer capacity and efficiency. The synchronizing is between the uLayer consolidation to the mLayer and the mBlock compaction process such that the smaller uLayer efficacy will not be reduced due to trapped uRegions that are less frequently updated.
    Type: Application
    Filed: September 29, 2022
    Publication date: April 4, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Marina FRID, Igor GENSHAFT
  • Patent number: 11853554
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a deallocation command corresponding to a plurality of deallocation requests, where each of the plurality of deallocation requests corresponds to a logical block address (LBA) range, determine that at least one of the plurality of deallocation requests is an unaligned deallocation request, generate a tag for metadata for the unaligned deallocation request, wherein the tag for the metadata includes a direction bit and a length bit, concatenate the metadata including the tag to an LBA range of the unaligned deallocation request, and complete the deallocation command using the metadata including the tag. Aligned deallocation requests are stored in a buffer. The concatenated unaligned deallocation requests are completed prior to completing the aligned deallocation requests from the buffer.
    Type: Grant
    Filed: April 5, 2022
    Date of Patent: December 26, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Galya Utevsky, Marina Frid, Igor Genshaft
  • Publication number: 20230409475
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to generate a first mapping portion and a second mapping portion, where the first mapping portion and the second mapping portion correspond to a same data set, and where the first mapping portion and the second mapping portion includes one or more parity bits, receive an update for the same data set, update the first mapping portion and the second mapping portion based on the update, where the second mapping portion is updated non-concurrently to updating the first mapping portion, and where the updating includes flipping a parity bit of the one or more parity bits, and determine whether the one or more parity bits of the first mapping portion matches the one or more parity bits of the second mapping portion.
    Type: Application
    Filed: June 16, 2022
    Publication date: December 21, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Vered KELNER, Marina FRID, Igor GENSHAFT
  • Publication number: 20230315296
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a deallocation command corresponding to a plurality of deallocation requests, where each of the plurality of deallocation requests corresponds to a logical block address (LBA) range, determine that at least one of the plurality of deallocation requests is an unaligned deallocation request, generate a tag for metadata for the unaligned deallocation request, wherein the tag for the metadata includes a direction bit and a length bit, concatenate the metadata including the tag to an LBA range of the unaligned deallocation request, and complete the deallocation command using the metadata including the tag. Aligned deallocation requests are stored in a buffer. The concatenated unaligned deallocation requests are completed prior to completing the aligned deallocation requests from the buffer.
    Type: Application
    Filed: April 5, 2022
    Publication date: October 5, 2023
    Applicants: Western Digital Technologies, Inc., Western Digital Technologies, Inc.
    Inventors: Galya UTEVSKY, Marina FRID, Igor GENSHAFT
  • Publication number: 20230280926
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to relocate first valid data from a first source block to a destination block, relocate second valid data from a second source block to the destination block, determine that the destination block is closed, re-mark the first and second source block with a second indication, and erase the source blocks that have the second indication. The first source block and the second source block are marked with a first indication after each respective data is relocated. The first indication indicates that the source block cannot be freed. The second indication indicates that the destination block is closed and the associated source blocks can be erased. Prior to closing the destination block, parity data may be generated for the data of the destination block and programmed to the destination block.
    Type: Application
    Filed: March 3, 2022
    Publication date: September 7, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Vered KELNER, Marina FRID, Igor GENSHAFT
  • Patent number: 11199983
    Abstract: In one or more embodiments, a NAND-based data storage device includes a device controller configured to receive a memory write command from a host specifying a set of memory locations to be written to, and to determine whether the command is for a random write. In response to the determination, the device controller is further configured to configure one or more update entries to an update layer of a mapping architecture of the device for the set of memory locations, such that the one or more update entries are respectively aligned with a size of a pre-defined MRU of mapping data for the device. By aligning the update entries with the smaller MRU, smaller regions of memory may be flagged as obsolete, increasing efficiency. In one embodiment, the device controller further includes a RAM, and the update layer is stored in the RAM.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: December 14, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Marina Frid, Igor Genshaft
  • Patent number: 10929224
    Abstract: A system and method for applying a first level of protection to data in a memory module include identifying a weak wordline from at least one of a plurality of blocks of the memory module. Each of the plurality of blocks includes a plurality of wordlines. The system and method also include determining that the weak wordline is to receive the first level of protection and applying the first level of protection to the weak wordline.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: February 23, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Avi Klein, Eran Sharon, Gadi Vishne, Igor Genshaft, Marina Frid, Michal Silbermintz
  • Publication number: 20210048948
    Abstract: In one or more embodiments, a NAND-based data storage device includes a device controller configured to receive a memory write command from a host specifying a set of memory locations to be written to, and to determine whether the command is for a random write. In response to the determination, the device controller is further configured to configure one or more update entries to an update layer of a mapping architecture of the device for the set of memory locations, such that the one or more update entries are respectively aligned with a size of a pre-defined MRU of mapping data for the device. By aligning the update entries with the smaller MRU, smaller regions of memory may be flagged as obsolete, increasing efficiency. In one embodiment, the device controller further includes a RAM, and the update layer is stored in the RAM.
    Type: Application
    Filed: August 12, 2019
    Publication date: February 18, 2021
    Inventors: Marina FRID, Igor GENSHAFT