Abstract: Apparatus, systems, methods, and computer program products are disclosed for logical address range mapping for storage devices. A system includes a set of non-volatile memory elements accessible using a set of physical addresses. A system includes a controller for a set of non-volatile memory elements. A controller is configured to maintain a hierarchical data structure comprising a plurality of levels for mapping logical addresses to a set of physical address. A controller is configured to receive an input/output (I/O) request. A controller is configured to translate a logical address for an I/O request to a physical address utilizing a largest mapped logical address range that includes the logical address in a hierarchical data structure. A level includes one or more mappings between logical address ranges and physical address ranges at a range size for the level.

Abstract: A system and method is disclosed for detecting and correcting for errors in mapping table information stored in volatile memory of a non-volatile memory system. The method may include checking for mapping entry errors when retrieving mapping data for the non-volatile memory from a volatile memory cache. When an error is discovered, the method includes the processor generating a set of candidate mapping entries each having a different single bit difference from the mapping entry discovered to have an error. Each candidate is tested against one or more mapping data accuracy tests and, when one of the candidates is found to be a correct mapping entry based on the one or more tests, the original mapping table entry with the determined defect is replaced with the successful candidate mapping entry.

Abstract: A system and method is described for managing mapping data in a non-volatile memory system having a volatile memory cache smaller than the update table for the mapping data. The system includes multiple mapping layers, for example two mapping layers, including a master mapping table of logical-to-physical mapping entries and an update table of mapping updates, for a non-volatile memory. A processor swaps predetermined size portions of the update mapping table and master mapping table into and out of the volatile memory cache based on host workload. The update mapping table portions may have a fixed or an adaptive logical range. Additional mapping layers, such as an expanded mapping layer having portions with a logical range greater than the logical range of the update mapping portions, may also be included and may be swapped into and out of the volatile memory with the master and update mapping table portions.

Abstract: An apparatus includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes an interface configured to send control information to a host device. The control information is associated with first parity information. The controller further includes a circuit configured to determine second parity information associated with the control information. The controller is configured to terminate and optionally rollback an operation associated with the control information in response to the first parity information differing from the second parity information. The terminated optionally rolled-back operation associated with the control information may be a non-blocking control sync operation.

Abstract: A device includes a schedule engine including a mode selection input. The schedule engine has an operating mode based on the mode selection input. The operating mode includes an opportunistic scheduling mode based on the mode selection input having a first value and a pipelined scheduling mode based on the mode selection input having a second value. The device further includes a buffer coupled to the schedule engine.

Abstract: A system and method is disclosed for detecting and correcting for errors in mapping table information stored in volatile memory of a non-volatile memory system. The method may include checking for mapping entry errors when retrieving mapping data for the non-volatile memory from a volatile memory cache. When an error is discovered, the method includes the processor generating a set of candidate mapping entries each having a different single bit difference from the mapping entry discovered to have an error. Each candidate is tested against one or more mapping data accuracy tests and, when one of the candidates is found to be a correct mapping entry based on the one or more tests, the original mapping table entry with the determined defect is replaced with the successful candidate mapping entry.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured, during execution of a relocation operation that includes storage of data to a memory buffer of an access device and retrieval of the data including data bits and first error correction code (ECC) parity bits from the memory buffer, to generate second ECC parity bits based on the data bits from the memory buffer and to compare the first ECC parity bits to the second ECC parity bits.

Abstract: A device includes a schedule engine including a mode selection input. The schedule engine has an operating mode based on the mode selection input. The operating mode includes an opportunistic scheduling mode based on the mode selection input having a first value and a pipelined scheduling mode based on the mode selection input having a second value. The device further includes a buffer coupled to the schedule engine.

Abstract: A data storage device includes a controller coupled to multiple groups of data storage dies, such as a meta-meta-die. The controller is configured to write data to a first meta-block if a storage size associated with a first group of data storage dies associated with a first priority is greater than or equal to a threshold storage size. The first meta-block includes a respective block of each data storage die of the first group. The controller is further configured to write the data to a second meta-block if the storage size associated with the first group is less than the threshold storage size. The second meta-block includes a respective block of each data storage die of the first group and further includes a respective block of each data storage die of the second group. Each data storage die of the second group is associated with a second priority.

Abstract: A data storage device includes a controller coupled to multiple groups of data storage dies, such as a meta-meta-die. The controller is configured to write data to a first meta-block if a storage size associated with a first group of data storage dies associated with a first priority is greater than or equal to a threshold storage size. The first meta-block includes a respective block of each data storage die of the first group. The controller is further configured to write the data to a second meta-block if the storage size associated with the first group is less than the threshold storage size. The second meta-block includes a respective block of each data storage die of the first group and further includes a respective block of each data storage die of the second group. Each data storage die of the second group is associated with a second priority.

Abstract: A method that may be performed by a data storage device includes configuring the data storage device to use a first scheduling scheme and, in response to detecting a trigger event, configuring the data storage device to use a second scheduling scheme. One of the first scheduling scheme and the second scheduling scheme is used to schedule performance of memory operations having the same operation type at a plurality of dies of a memory of the data storage device. The other of the first scheduling scheme and the second scheduling scheme is used to schedule memory operations opportunistically.

Abstract: A device includes a schedule engine including a mode selection input. The schedule engine has an operating mode based on the mode selection input. The operating mode includes an opportunistic scheduling mode based on the mode selection input having a first value and a pipelined scheduling mode based on the mode selection input having a second value. The device further includes a buffer coupled to the schedule engine.

Abstract: Apparatus and methods implemented therein are disclosed for storing data in flash memories. The apparatus comprises a flash memory having several physical blocks, a logical to virtual mapping table, a virtual to physical mapping table and a memory controller. The memory controller retrieves a virtual block address from the logical to virtual mapping table. The virtual block address corresponds to an entry in the virtual to physical mapping table. The entry in the virtual to physical mapping table contains a reference to a physical block. The memory controller uses the virtual block address to retrieve the reference to the physical block and stores data in the physical block. The memory controller copies the stored data from the physical block to a second physical block. The memory controller then replaces the reference to the physical block contained in the entry of the virtual to physical mapping table with a reference to the second physical block.

Abstract: A system and method for request verification in an Application Level Gateway (ALG) located between a client and a server in a data transmission network. The ALG receives from a server a message that requires some responsive actions from a client. The ALG adds to this message Verification Data (VD) that includes information about expected actions required from the client. The ALG then sends the message with the above-mentioned additions to the client. The client receives this message and sends a response, with the actual actions and with the VD, to the server. The ALG obtains this response with the VD, and compares the description of the expected actions with actual actions of the client. If the actions of the client are legitimate, the ALG sends the client response to the server.

Abstract: An Application Level Gateway (ALG) based on an universal parser, in a data transmission network. This ALG enables all data flow of an application level protocol to be checked for concordance with the formal syntax description of the data transmission protocol, and with a security policy. The ALG contains a transmission controller, universal parser, and at least one parser plug-in for each universal parser. This parser plug-in is specific to the data transmission protocol, and can be automatically created from the formal syntax description of a data transmission protocol. A security policy (rules, restrictions) can be implemented in the parser plug-in and/or in the settings.

Abstract: A system and method for request verification in an Application Level Gateway (ALG) located between a client and a server in a data transmission network. The ALG receives from a server a message that requires some responsive actions from a client. The ALG adds to this message Verification Data (VD) that includes information about expected actions required from the client. The ALG then sends the message with the above-mentioned additions to the client. The client receives this message and sends a response, with the actual actions and with the VD, to the server. The ALG obtains this response with the VD, and compares the description of the expected actions with actual actions of the client. If the actions of the client are legitimate, the ALG sends the client response to the server.