Patents by Inventor Igor Kasko
Igor Kasko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8284596Abstract: An integrated circuit includes an array of diodes and an electrode coupled to each diode. The integrated circuit includes a layer of resistance changing material coupled to the electrodes and bit lines coupled to the layer of resistance changing material. The layer of resistance changing material provides a resistance changing element at each intersection of each electrode and each bit line.Type: GrantFiled: June 9, 2008Date of Patent: October 9, 2012Assignee: Qimonda AGInventors: Igor Kasko, Thomas Happ, Andreas Walter, Stefan Tegen, Peter Baars, Klaus Muemmler
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Publication number: 20090303780Abstract: An integrated circuit includes an array of diodes and an electrode coupled to each diode. The integrated circuit includes a layer of resistance changing material coupled to the electrodes and bit lines coupled to the layer of resistance changing material. The layer of resistance changing material provides a resistance changing element at each intersection of each electrode and each bit line.Type: ApplicationFiled: June 9, 2008Publication date: December 10, 2009Applicant: Qimonda AGInventors: Igor Kasko, Thomas Happ, Andreas Walter, Stefan Tegen, Peter Baars, Klaus Muemmler
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Publication number: 20090267042Abstract: According to one embodiment of the present invention, an integrated circuit including a plurality of resistance changing memory cells is provided. Each memory cell includes: a semiconductor substrate; a select device arranged within the semiconductor substrate; and a memory element being arranged above the semiconductor substrate. The select device is a diode comprising a first semiconductor area of a first conductive type and a second semiconductor area of a second conductive type which are arranged adjacent to each other such that a lateral pn-junction is formed. The first semiconductor area is connected to a word line arranged on or above the semiconductor substrate. The second semiconductor area is connected to the memory element via a conductive connection element.Type: ApplicationFiled: April 24, 2008Publication date: October 29, 2009Inventors: Thomas D. Happ, Igor Kasko, Andreas Walter
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Publication number: 20090073743Abstract: A method of fabricating a memory cell including a solid electrolyte layer doped with metallic material and an electrode layer arranged above the solid electrolyte layer. The method includes doping a solid electrolyte layer with metallic material and forming an electrode layer above the solid electrolyte layer, wherein doping the solid electrolyte layer is carried out before forming the electrode layer.Type: ApplicationFiled: September 17, 2007Publication date: March 19, 2009Inventors: Igor Kasko, Michael Kund
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Publication number: 20070194301Abstract: One aspect of the invention relates to a semiconductor arrangement having at least one nonvolatile memory cell which has a first electrode comprising at least two layers; and having an organic material, the organic material forming a compound with that layer of the first electrode which is in direct contact. One aspect of the invention furthermore relates to a method for producing the nonvolatile memory cell, a semiconductor arrangement having a plurality of memory cells according to the invention, and a method for producing the same.Type: ApplicationFiled: November 24, 2004Publication date: August 23, 2007Inventors: Recai Sezi, Andreas Walter, Reimund Engl, Anna Maltenberger, Christine Dehm, Sitaram Arkalgud, Igor Kasko, Joachim Nuetzel, Jakob Kriz, Thomas Mikolajick, Cay-Uwe Pinnow
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Patent number: 6985384Abstract: A magneto resistive memory device is fabricated by etching a blanket metal stack comprised of a buffer layer, pinned magnetic layer, a tunnel barrier layer and a free magnetic layer. The problem of junction shorting from resputtered metal during the etching process is eliminated by formation of a protective spacer covering the side of the freelayer and tunnel barrier interface. The spacer is formed following the first etch through the free layer which stops on the barrier layer. After spacer formation a second etch is made to isolate the device. The patterning of the device tunnel junction is made using a disposable mandrel method that enables a self-aligned contact to be made following the completion of the device patterning process.Type: GrantFiled: October 1, 2002Date of Patent: January 10, 2006Assignee: International Business Machines CorporationInventors: Gregory Costrini, John Hummel, Kia-Seng Low, Igor Kasko, Frank Findeis, Wolfgang Raberg
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Patent number: 6875652Abstract: The invention relates to a method for producing ferroelectric capacitors that are structured using the stack principle and that are used in integrated semiconductor memory chips. The individual capacitor modules have an oxygen barrier between a lower capacitor electrode and an electrically conductive plug. At a site where it is not covered by the corresponding oxygen barrier, an unstructured adhesive layer is oxidized by the oxygen arising during the tempering process of the ferroelectric and forms insulating segments at the site in such a way that the lower capacitor electrodes of the ferroelectric capacitors are electrically insulated from one another. This makes it possible to dispense with structuring the adhesive layer. Furthermore, the layer serves as a getter of oxygen and inhibits the diffusion of oxygen to the plug.Type: GrantFiled: August 11, 2003Date of Patent: April 5, 2005Assignee: Infineon Technologies AGInventors: Igor Kasko, Matthias Kroenke, Thomas Mikolajick
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Patent number: 6852240Abstract: A ferroelectric capacitor configuration is configured with at least two different coercitive voltages. A first electrode structure having a surface which forms at least two levels is firstly produced. A layer of ferroelectric material of varying thickness is deposited over the first electrode by spin coating. A second electrode structure is subsequently formed on the layer of ferroelectric material.Type: GrantFiled: February 26, 2001Date of Patent: February 8, 2005Assignee: Infineon Technologies AGInventors: Walter Hartner, Günther Schindler, Volker Weinrich, Igor Kasko
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Patent number: 6818503Abstract: A method of fabricating semiconductor memory devices is simplified by providing at least some plug regions, which are provided for contacting storage capacitor devices of a capacitor configuration, such that the plug regions have in each case a region that is elevated above the surface region of a passivation region.Type: GrantFiled: July 1, 2002Date of Patent: November 16, 2004Assignee: Infineon Technologies AGInventors: Rainer Bruchhaus, Gerhard Enders, Walter Hartner, Igor Kasko, Matthias Krönke, Thomas Mikolajick, Nicolas Nagel, Michael Röhner, Volker Weinrich
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Patent number: 6806097Abstract: Ferroelectric memory cells are produced according to the stack principle. An adhesive layer is formed between a capacitor electrode of a memory capacitor and a conductive plug. An oxygen diffusion barrier is formed above the adhesive layer and once the ferroelectric has been deposited, the adhesive layer and the barrier are subjected to rapid thermal processing (RTP) in an oxygen atmosphere. An oxygen rate of the adhesive layer and the diffusion coefficient of oxygen in the material of the adhesive layer dependent on the temperature are determined. A diffusion coefficient of silicon in the material of the adhesive layer, dependent on the temperature, is determined. A temperature range for the RTP step from the two diffusion coefficients, determined for a predetermined layer thickness and layer width of the adhesive layer and the oxygen diffusion barrier is calculated, therefore, the siliconization of the adhesive layer occurs more rapidly than its oxidation.Type: GrantFiled: September 23, 2003Date of Patent: October 19, 2004Assignee: Infineon Technologies AGInventors: Matthias Kroenke, Igor Kasko
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Publication number: 20040185578Abstract: The invention relates to a method for producing ferroelectric capacitors that are structured using the stack principle and that are used in integrated semiconductor memory chips. The individual capacitor modules have an oxygen barrier between a lower capacitor electrode and an electrically conductive plug. At a site where it is not covered by the corresponding oxygen barrier, an unstructured adhesive layer is oxidized by the oxygen arising during the tempering process of the ferroelectric and forms insulating segments at the site in such a way that the lower capacitor electrodes of the ferroelectric capacitors are electrically insulated from one another. This makes it possible to dispense with structuring the adhesive layer. Furthermore, the layer serves as a getter of oxygen and inhibits the diffusion of oxygen to the plug.Type: ApplicationFiled: August 11, 2003Publication date: September 23, 2004Inventors: Igor Kasko, Matthias Kroenke, Thomas Mikolajick
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Publication number: 20040157345Abstract: Ferroelectric memory cells are produced according to the stack principle. An adhesive layer is formed between a capacitor electrode of a memory capacitor and a conductive plug. An oxygen diffusion barrier is formed above the adhesive layer and once the ferroelectric has been deposited, the adhesive layer and the barrier are subjected to rapid thermal processing (RTP) in an oxygen atmosphere. An oxygen rate of the adhesive layer and the diffusion coefficient of oxygen in the material of the adhesive layer dependent on the temperature are determined. A diffusion coefficient of silicon in the material of the adhesive layer, dependent on the temperature, is determined. A temperature range for the RTP step from the two diffusion coefficients, determined for a predetermined layer thickness and layer width of the adhesive layer and the oxygen diffusion barrier is calculated, therefore, the siliconization of the adhesive layer occurs more rapidly than its oxidation.Type: ApplicationFiled: September 23, 2003Publication date: August 12, 2004Inventors: Matthias Kroenke, Igor Kasko
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Publication number: 20040021188Abstract: A semiconductor device (100) and method of fabrication thereof, wherein a plurality of first conductive lines (116) are formed in a dielectric layer (112) over a substrate (110), and an insulating cap layer (140) is disposed over the first conductive lines (116) and exposed portions of the dielectric layer (112). The insulating cap layer (140) is patterned and etched to expose stack portions of the first conductive lines (116). A conductive cap layer (144) is deposited over the exposed portions of the first conductive lines (116). A magnetic material stack (118) is disposed over the insulating cap layer (140), and the magnetic material stack is etched to form magnetic stacks. The insulating cap layer (140) and conductive cap layer (144) protect the underlying first conductive line (116) material during the etching processes.Type: ApplicationFiled: July 31, 2002Publication date: February 5, 2004Applicants: Infineon Technologies North America Corp., International Business Machines CorporationInventors: Kia-Seng Low, John P. Hummel, Igor Kasko, Gregory Costrini
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Patent number: 6686265Abstract: A capacitor electrode is produced with an underlying barrier structure. A barrier incorporation layer is used and a CMP (chemical mechanical polishing) process is employed in order to produce the barrier structure. The capacitor electrode with an underlying barrier structure is produced by depositing a barrier layer on a semiconductor substrate; forming a barrier structure from the barrier layer with a lithographic mask and an etching step; depositing a barrier incorporation layer covering the barrier structure and surrounding regions; and removing the barrier incorporation layer with chemical mechanical polishing until the barrier structure is uncovered, to thereby form the capacitor electrode above the barrier structure.Type: GrantFiled: April 22, 2002Date of Patent: February 3, 2004Assignee: Infineon Technologies AGInventors: Gerhard Beitel, Annette Sänger, Igor Kasko
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Patent number: 6680500Abstract: A semiconductor device (100) and method of fabrication thereof, wherein a plurality of first conductive lines (116) are formed in a dielectric layer (112) over a substrate (110), and an insulating cap layer (140) is disposed over the first conductive lines (116) and exposed portions of the dielectric layer (112). The insulating cap layer (140) is patterned and etched to expose stack portions of the first conductive lines (116). A conductive cap layer (144) is deposited over the exposed portions of the first conductive lines (116). A magnetic material stack (118) is disposed over the insulating cap layer (140), and the magnetic material stack is etched to form magnetic stacks. The insulating cap layer (140) and conductive cap layer (144) protect the underlying first conductive line (116) material during the etching processes.Type: GrantFiled: July 31, 2002Date of Patent: January 20, 2004Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Kia-Seng Low, John P. Hummel, Igor Kasko, Gregory Costrini
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Patent number: 6573542Abstract: The invention relates to a microelectronic structure. In the structure, an oxygen-containing iridium layer is embedded between a silicon-containing layer and an oxygen barrier layer. The iridium layer is especially produced by a sputter process in an oxygen atmosphere with a low oxygen content. The oxygen-containing iridium layer is stale at temperatures up to 800° C. and withstands the formation of iridium silicide upon contact with the silicon-containing layer. Such micro-electronic structures are preferably used in semiconductor memories.Type: GrantFiled: June 25, 2001Date of Patent: June 3, 2003Assignee: Infineon Technologies AGInventors: Rainer Bruchhaus, Nicolas Nagel, Hermann Wendt, Igor Kasko, Robert Primig
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Publication number: 20030060002Abstract: A method of fabricating semiconductor memory devices is simplified by providing at least some plug regions, which are provided for contacting storage capacitor devices of a capacitor configuration, such that the plug regions have in each case a region that is elevated above the surface region of a passivation region.Type: ApplicationFiled: July 1, 2002Publication date: March 27, 2003Inventors: Rainer Bruchhaus, Gerhard Enders, Walter Hartner, Igor Kasko, Matthias Kronke, Thomas Mikolajick, Nicolas Nagel, Michael Rohner, Volker Weinrich
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Patent number: 6495415Abstract: A method for fabricating a patterned layer from a layer material. The method includes steps of: providing a substrate with at least one target region and at least one migration region; applying a layer material; adding a material to the layer material; and performing a heat treatment such that the layer material migrates from the migration region to the target region and a layer which is self-aligned and self-patterned with respect to the target region is formed. The method has the advantage that the layer material, which can often only be etched with difficulty, does not have to be patterned directly. The desired structure of the layer is predetermined by preliminarily structuring the substrate into a target region and a migration region, and is produced by the migration of the layer material as a result of the heat treatment.Type: GrantFiled: December 26, 2001Date of Patent: December 17, 2002Assignee: Infineon Technologies AGInventors: Walter Hartner, Igor Kasko, Volker Weinrich, Frank Hintermaier, Günther Schindler, Hermann Wendt
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Publication number: 20020151162Abstract: A capacitor electrode is produced with an underlying barrier structure. A barrier incorporation layer is used and a CMP (chemical mechanical polishing) process is employed in order to produce the barrier structure.Type: ApplicationFiled: April 22, 2002Publication date: October 17, 2002Inventors: Gerhard Beitel, Annette Sanger, Igor Kasko
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Publication number: 20020086511Abstract: A method for fabricating a patterned layer from a layer material. The method includes steps of: providing a substrate with at least one target region and at least one migration region; applying a layer material; adding a material to the layer material; and performing a heat treatment such that the layer material migrates from the migration region to the target region and a layer which is self-aligned and self-patterned with respect to the target region is formed. The method has the advantage that the layer material, which can often only be etched with difficulty, does not have to be patterned directly. The desired structure of the layer is predetermined by preliminarily structuring the substrate into a target region and a migration region, and is produced by the migration of the layer material as a result of the heat treatment.Type: ApplicationFiled: December 26, 2001Publication date: July 4, 2002Inventors: Walter Hartner, Igor Kasko, Volker Weinrich, Frank Hintermaier, Gunther Schindler, Hermann Wendt