Abstract: A clock driver in a semiconductor memory device does not output a rising edge clock signal and a falling edge clock signal outputted from a DLL circuit when there are no data transmitted to a data output pin in a read operation. A clock driver which can reduce current consumption by suppressing output of a rising edge clock signal and a falling edge clock signal in a stand-by mode in a semiconductor memory device. The clock driver for use in a semiconductor memory device according to the present invention does not output a rising edge clock signal and a falling edge clock signal outputted from a DLL circuit when there is no data transmitted to a data output pin in a read operation.

Abstract: Disclosed is a semiconductor memory device divided into a core region where memory cells are formed and a peripheral region where an input/output line circuit is formed. Particularly, the input/output line circuit of the semiconductor memory device can be operated without affecting other external devices and being affected by noise from other external devices along with improved power dissipation. The semiconductor memory device includes: a core voltage generator for supplying a core voltage to the core region as a driving voltage; an internal voltage generator for supplying an internal voltage to the peripheral region as a driving voltage; and a line voltage generator for supplying a line voltage to the input/output line circuit as a driving voltage. In this manner, a stable supply of the driving voltage is achieved.

Abstract: There is provided a multi-port memory device, which is capable of preventing a first high data fail phenomenon at an initial operation in a current sensing type global data bus transmission/reception structure without causing a problem in a low data transmission. In the multi-port memory device having a data transmission/reception block (bank, port, global data bus connection block, etc.) which exchanges data with the global data bus in a current sensing type data transmission/reception structure, an initialization switch is used to discharge each global data bus line and an initialization signal generator controls the initialization switch. A first high data fail at the initial operation is caused by a high precharge level of the global data bus. According to the present invention, it is possible to lower a high precharge level without causing a problem in data transmission.

Abstract: There is provided a multi-port memory device having a serial I/O interface, which is capable of providing an operation test without any collision with an internal command/address generation path through a limited external pin. The multi-port memory device includes a plurality of ports supporting a serial I/O interface, and the plurality of ports includes a transmission pad and a reception pad.

Abstract: A multi-port memory device can avoid failure of the first high data during initial operation so that reliability and operation characteristic of the memory device can be improved. The multi-port memory device comprises a global data bus having a multiplicity of bus lines, a plurality of banks having a current sensing type transceiving structure for exchanging data with the global data bus, one or more ports having a current sensing type transceiving structure for exchanging data with the global data bus, a plurality of switches, each arranged between the corresponding bank and the bus lines of the global data bus for selectively connecting one of a redundant column and normal columns of the corresponding bank to the global data bus, and a controlling unit for restricting the turn-on period of the switches to the substantial operation period of the corresponding bank.

Abstract: A semiconductor memory device having sense amplifier array blocks between neighboring unit memory cell array blocks in a column direction, the semiconductor memory device includes a first sense amplifier driving line configured by passing the sense amplifiers in a row direction, a second sense amplifier driving line configured by passing the sense amplifiers in a row direction, a plurality of first NMOS transistors, which is disposed in the sense amplifier array block, for locally performing a pull-up operation of the first sense amplifier driving line in response to a first control signal, and a second NMOS transistor, which is disposed in a hole area, for performing a pull-down operation of the second sense amplifier driving line in response to a second control signal.

Abstract: The present invention relates to a semiconductor memory device. A voltage generator for supplying a sense amplifier I/O voltage (VSIO) and a voltage generator for supplying a bit line precharge voltage (VBLP) are independently separated. It is possible to prevent the bit line precharge voltage (VBLP) from increasing when the sense amplifier I/O voltage (VSIO) is increased due to the introduction of a column reset voltage (VCORE).

Abstract: A semiconductor memory device having sense amplifier array blocks between neighboring unit memory cell array blocks in a column direction, the semiconductor memory device includes a first sense amplifier driving line configured by passing the sense amplifiers in a row direction, a second sense amplifier driving line configured by passing the sense amplifiers in a row direction, a plurality of first NMOS transistors, which is disposed in the sense amplifier array block, for locally performing a pull-up operation of the first sense amplifier driving line in response to a first control signal, and a second NMOS transistor, which is disposed in a hole area, for performing a pull-down operation of the second sense amplifier driving line in response to a second control signal.

Abstract: The present invention relates to a semiconductor memory device. A voltage generator for supplying a sense amplifier I/O voltage (VSIO) and a voltage generator for supplying a bit line precharge voltage (VBLP) are independently separated. It is possible to prevent the bit line precharge voltage (VBLP) from increasing when the sense amplifier I/O voltage (VSIO) is increased due to the introduction of a column reset voltage (VCORE).

Abstract: The present invention provides a semiconductor memory device for reducing power consumption by turning off a DLL clock tree in stand-by mode. The synchronous semiconductor memory device in accordance with the present invention includes a clock synchronization means for synchronizing a data output with a external clock; and a clock tree on/off control means for delaying an enable timing of a RAS idle signal for a predetermined time after a row inactive instruction is supplied, turning on/off a clock tree of the clock synchronization means in response to the RAS idle signal.

Abstract: The present invention provides a semiconductor memory device for reducing power consumption by turning off a DLL clock tree in stand-by mode. The synchronous semiconductor memory device in accordance with the present invention includes a clock synchronization means for synchronizing a data output with a external clock; and a clock tree on/off control means for delaying an enable timing of a RAS idle signal for a predetermined time after a row inactive instruction is supplied, turning on/off a clock tree of the clock synchronization means in response to the RAS idle signal.

Abstract: A clock driver in a semiconductor memory device does not output a rising edge clock signal and a falling edge clock signal outputted from a DLL circuit when there are no data transmitted to a data output pin in a read operation.

Abstract: A memory device includes: a plurality of cell array blocks provided with a plurality of memory cells coupled to a word line and a bit line pair; a bit line control block including a first control block and a second control block, wherein the first control block is separately coupled to a first bit line pair coupled to a first cell array block among the cell array blocks, and the second control block is shared with a second bit line pair commonly coupled to the first cell array block and a second cell array block adjacent to the first cell array block; and a precharge reinforcement unit, coupled to a predetermined portion of the first control block, for reducing a precharge speed difference between the first bit line pair and the second bit line pair.

Abstract: The data access device of a dynamic random access memory includes a plurality of bit line sensing amplifiers, decoders, and column sensing amplifiers. The plurality of bit line sensing amplifiers amplify a data signal and inverted data signal applied to a bit line and inverted bit line, respectively. The plurality of decoders each receive an inverted pulse signal and an associated code signal. Each decoder generates an enable signal based on the inverted pulse signal and the associated code signal. Each decoder includes a first and second NMOS transistor. Each of the column sensing amplifiers is associated with one of the decoders and one of the bit line sensing amplifiers, and each of the column sensing amplifiers selectively loads the data signal and inverted data signal of the associated bit line sensing amplifier on a first and second data bus, respectively, based on the enable signal from the associated decoder. Each column sensing amplifier includes a third and fourth NMOS transistor.