Patents by Inventor Ik-Soo Eo
Ik-Soo Eo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11481470Abstract: Provided is a fast Fourier transform device for analyzing specific frequency components of an input signal. The fast Fourier transform device includes an address generator that generates an address, based on a first frequency index corresponding to a first frequency, an FFT coefficient table that outputs a first Fourier transform coefficient corresponding to the generated address among Fourier transform coefficients of the first frequency index, and an operator that calculates a frequency characteristic of an input signal associated with the first frequency, based on the input signal and the first Fourier transform coefficient.Type: GrantFiled: June 10, 2020Date of Patent: October 25, 2022Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Youngseok Baek, Ik Soo Eo, Bon Tae Koo
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Patent number: 11067679Abstract: Provided is a narrow-band radar device including an orthogonal code generator configured to generate a plurality of orthogonal generators, a pseudo-noise code generator configured to generate a plurality of pseudo-noise codes, a radar transmitter configured to spread-modulate transmission data using the plurality of orthogonal codes and pseudo-noise codes, and a radar receiver configured to demodulate a reception signal using the plurality of orthogonal codes and pseudo-noise codes, and calculate at least one of an azimuth angle, elevation angel, speed, or range of a target from the demodulated reception signal.Type: GrantFiled: April 18, 2018Date of Patent: July 20, 2021Assignee: Electronics and Telecommunications Research InstituteInventors: Ik Soo Eo, Bon Tae Koo
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Publication number: 20200394251Abstract: Provided is a fast Fourier transform device for analyzing specific frequency components of an input signal. The fast Fourier transform device includes an address generator that generates an address, based on a first frequency index corresponding to a first frequency, an FFT coefficient table that outputs a first Fourier transform coefficient corresponding to the generated address among Fourier transform coefficients of the first frequency index, and an operator that calculates a frequency characteristic of an input signal associated with the first frequency, based on the input signal and the first Fourier transform coefficient.Type: ApplicationFiled: June 10, 2020Publication date: December 17, 2020Applicant: Electronics and Telecommunications Research InstituteInventors: Youngseok BAEK, Ik Soo EO, Bon Tae KOO
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Publication number: 20180348355Abstract: Provided is a narrow-band radar device including an orthogonal code generator configured to generate a plurality of orthogonal generators, a pseudo-noise code generator configured to generate a plurality of pseudo-noise codes, a radar transmitter configured to spread-modulate transmission data using the plurality of orthogonal codes and pseudo-noise codes, and a radar receiver configured to demodulate a reception signal using the plurality of orthogonal codes and pseudo-noise codes, and calculate at least one of an azimuth angle, elevation angel, speed, or range of a target from the demodulated reception signal.Type: ApplicationFiled: April 18, 2018Publication date: December 6, 2018Applicant: Electronics and Telecommunications Research InstituteInventors: Ik Soo EO, Bon Tae KOO
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Patent number: 9780891Abstract: A method and device for calibrating a DC offset and an I-Q imbalance component of an RF transceiver, the method including inputting a test signal into a transmitter, and converting the test signal into an analogue test signal; converting the analogue test signal using a transmitting mixer; sub-sampling a signal output from the transmitting mixer; and computing a DC offset calibrating constant number and an I-Q imbalance calibrating constant number from a sub-sampled signal.Type: GrantFiled: August 5, 2016Date of Patent: October 3, 2017Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Ik Soo Eo, Sang-Kyun Kim, Cheon Soo Kim, Jang Hong Choi
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Publication number: 20170257176Abstract: A method and device for calibrating a DC offset and an I-Q imbalance component of an RF transceiver, the method including inputting a test signal into a transmitter, and converting the test signal into an analogue test signal; converting the analogue test signal using a transmitting mixer; sub-sampling a signal output from the transmitting mixer; and computing a DC offset calibrating constant number and an I-Q imbalance calibrating constant number from a sub-sampled signal.Type: ApplicationFiled: August 5, 2016Publication date: September 7, 2017Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Ik Soo EO, Sang-Kyun Kim, Cheon Soo KIM, Jang Hong CHOI
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Patent number: 9509283Abstract: Disclosed is an interpolation filter based on time assignment algorithm. An interpolation filter comprises an enable signal generating part generating enable signals for operation of the interpolation filter, an input value generating part generating input values, a first calculating part generating a first output value based on a first enable signal and a first input value, a second calculating part generating a second output value based on a second enable signal and a second input value, and an output value selecting part selecting a final output value among the first output value and the second output value. Thus, continuity of output data can be guaranteed, and hardware can be shared by using time assignment algorithm so that a total size of the interpolation filter can be reduced.Type: GrantFiled: May 14, 2014Date of Patent: November 29, 2016Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Mi Jeong Park, Jang Hong Choi, Ik Soo Eo
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Patent number: 9379886Abstract: A sample rate converter and a method of converting a sample rate are disclosed herein. The sample rate converter includes a data delay unit, a clock rate conversion unit, a Lagrange polynomial filter unit, a resample position calculation unit, and a resample position compensation unit. The data delay unit delays signals in response to an input clock signal. The clock rate conversion unit converts the sample rate of the signals. The Lagrange polynomial filter unit performs a filtering function on the signals whose rate has been converted. The resample position calculation unit outputs the value (Dint, dfrac) of the resample position of the signals based on a set resample ratio value. The resample position compensation unit corrects the error value of the signals by applying the value (Dint, dfrac) to the signals, and outputs a final signal.Type: GrantFiled: July 7, 2015Date of Patent: June 28, 2016Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Sang-Kyun Kim, Mi-Jeong Park, Ik-Soo Eo
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Publication number: 20160087787Abstract: A sample rate converter and a method of converting a sample rate are disclosed herein. The sample rate converter includes a data delay unit, a clock rate conversion unit, a Lagrange polynomial filter unit, a resample position calculation unit, and a resample position compensation unit. The data delay unit delays signals in response to an input clock signal. The clock rate conversion unit converts the sample rate of the signals. The Lagrange polynomial filter unit performs a filtering function on the signals whose rate has been converted. The resample position calculation unit outputs the value (Dint, dfrac) of the resample position of the signals based on a set resample ratio value. The resample position compensation unit corrects the error value of the signals by applying the value (Dint, dfrac) to the signals, and outputs a final signal.Type: ApplicationFiled: July 7, 2015Publication date: March 24, 2016Inventors: Sang-Kyun KIM, Mi-Jeong PARK, Ik-Soo EO
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Patent number: 9294135Abstract: A digital RF receiver does not use a separate receiver according to a mode and a band for multi-mode reception, MIMO reception, and bandwidth extension reception, and changes only setting variables in a single receiver structure so as to implement multi-mode reception, MIMO reception, bandwidth extension reception, and/or simultaneous multi-mode operation, such that complexity of the receiver, development cost, and power consumption can be reduced.Type: GrantFiled: September 11, 2012Date of Patent: March 22, 2016Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Ik Soo Eo, Sang-Kyun Kim, Mun Yang Park, Seon-Ho Han, Hyun Kyu Yu
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Patent number: 9276800Abstract: The present invention relates to a single frequency synthesizer based FDD transceiver. A single frequency synthesizer generates and provides a carrier frequency so that frequency up-conversion and frequency down-conversion can be performed at the time of transmission and reception. Accordingly, the area, power consumption, and design complexity of the entire system can be reduced, and the performance of the system can be improved.Type: GrantFiled: September 10, 2012Date of Patent: March 1, 2016Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Hyun Ho Boo, Seon-Ho Han, Jang Hong Choi, Ik Soo Eo, Hyun Kyu Yu
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Patent number: 9270502Abstract: Embodiments provide a digital RF receiver including a signal converting unit which converts an RF signal received from an external device into a digital signal, a plurality of functional modules which processes the digital signal in accordance with a predetermined algorithm when the digital signal is input, and a signal processing controller which selects at least one of the plurality of functional modules to control the digital signal to be processed in consideration of whether an IF signal component is included in the digital signal or a sampling rate related with sampling information of the digital signal.Type: GrantFiled: August 6, 2013Date of Patent: February 23, 2016Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Ik Soo Eo, Sang Kyun Kim, Seon Ho Han
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Patent number: 9013347Abstract: An embodiment of the present invention relates to a radar apparatus, wherein a distance to a target and a velocity of the target are measured by transmitting a digitally modulated transmitting signal using a digital code and receiving and demodulating an echo signal returned due to reflection of the transmitting signal from the target.Type: GrantFiled: April 12, 2012Date of Patent: April 21, 2015Assignee: Electronics and Telecommunications Research InstituteInventors: Pil Jae Park, Cheon Soo Kim, Hyun Kyu Yu, Min Park, Ik Soo Eo
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Publication number: 20150097708Abstract: A data rate conversion device generates a first parameter representing a memory address position to sample and a second parameter representing a phase value of an estimation time point, records input data at a memory based on an input clock, outputs sampled continued data from the memory using the first parameter based on an output clock, and generates and outputs final data using the continued data, a plurality of filter coefficients, and the second parameter.Type: ApplicationFiled: March 12, 2014Publication date: April 9, 2015Applicant: Electronics and Telecommunications Research InstituteInventors: Mi Jeong PARK, Ik Soo EO, Sang-Kyun KIM
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Patent number: 9000958Abstract: A data rate conversion device generates a first parameter representing a memory address position to sample and a second parameter representing a phase value of an estimation time point, records input data at a memory based on an input clock, outputs sampled continued data from the memory using the first parameter based on an output clock, and generates and outputs final data using the continued data, a plurality of filter coefficients, and the second parameter.Type: GrantFiled: March 12, 2014Date of Patent: April 7, 2015Assignee: Electronics and Telecommunications Research InstituteInventors: Mi Jeong Park, Ik Soo Eo, Sang-Kyun Kim
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Publication number: 20150019607Abstract: Disclosed is an interpolation filter based on time assignment algorithm. An interpolation filter comprises an enable signal generating part generating enable signals for operation of the interpolation filter, an input value generating part generating input values, a first calculating part generating a first output value based on a first enable signal and a first input value, a second calculating part generating a second output value based on a second enable signal and a second input value, and an output value selecting part selecting a final output value among the first output value and the second output value. Thus, continuity of output data can be guaranteed, and hardware can be shared by using time assignment algorithm so that a total size of the interpolation filter can be reduced.Type: ApplicationFiled: May 14, 2014Publication date: January 15, 2015Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: MI JEONG PARK, JANG HONG CHOI, IK SOO EO
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Patent number: 8873687Abstract: The present invention relates to a digital front end receiver using a DC offset compensation scheme. The digital front end receiver includes a DC offset compensation filter configured to remove DC offset components from signals received from a digital mixer and a Cascaded Integrator-Comb (CIC) decimation filter configured to reduce a sampling rate of the signals received from the DC offset compensation block.Type: GrantFiled: September 11, 2012Date of Patent: October 28, 2014Assignee: Electronics and Telecommunications Research InstituteInventors: Sang-Kyun Kim, Ik Soo Eo, Hyun Kyu Yu
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Patent number: 8693581Abstract: Disclosed is a method for receiving an analog signal from a receiver supporting at least a first channel band and a second channel band. The method for receiving an analog signal includes sampling the analog signal received through an antenna, generating a decimated signal by passing the sampled signal to a CIC decimation filter; and inputting the decimated signal to a channel selection filter.Type: GrantFiled: October 28, 2011Date of Patent: April 8, 2014Assignee: Electronics & Telecommunications Research InstituteInventors: Sang-Kyun Kim, Ik Soo Eo, Mijeong Park, Hyun Kyu Yu
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Publication number: 20140044221Abstract: Embodiments provide a digital RF receiver including a signal converting unit which converts an RF signal received from an external device into a digital signal, a plurality of functional modules which processes the digital signal in accordance with a predetermined algorithm when the digital signal is input, and a signal processing controller which selects at least one of the plurality of functional modules to control the digital signal to be processed in consideration of whether an IF signal component is included in the digital signal or a sampling rate related with sampling information of the digital signal.Type: ApplicationFiled: August 6, 2013Publication date: February 13, 2014Applicant: Electronics and Telecommunications Research InstituteInventors: Ik Soo EO, Sang Kyun Kim, Seon Ho Han
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Publication number: 20130163699Abstract: The present invention relates to a digital front end receiver using a DC offset compensation scheme. The digital front end receiver includes a DC offset compensation filter configured to remove DC offset components from signals received from a digital mixer and a Cascaded Integrator-Comb (CIC) decimation filter configured to reduce a sampling rate of the signals received from the DC offset compensation block.Type: ApplicationFiled: September 11, 2012Publication date: June 27, 2013Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Sang-Kyun Kim, Ik Soo Eo, Hyun Kyu Yu