Abstract: A region searcher, a method of driving the same, and a code searcher using the same are disclosed. When a predetermined region is iteratively searched, the energy value corresponding to the same hypothesis location value is stored by using a searcher having divided two buffers, thereby the implementation complexity thereof can be remarkably reduced, without using a simple memory. In addition, in case where the region is iteratively searched in the state of the deteriorated signal-to-noise ratio to find the energy value at one hypothesis location and in case where the region must be iteratively searched because of the restriction which the size of the matched filter can be not increased, the implementation complexity thereof can be remarkably reduced.

Abstract: A multipath searching device includes a radio front-end for converting a received radio signal into a baseband signal and for outputting the baseband signal. A profile calculating unit is included for calculating and outputting the multipath profile of the baseband signal. A first detector determines whether or not the radio signal traveled along a multipath is having a short-delay path by comparing the peak value of the multipath profile with a profile value of a predetermined position time interval before or after the peak of the multipath profile. A path selector receives the multipath profile and the detection result of the first detector, generates time delay information for each path, and separates many paths along which the radio signal traveled. A receiving unit receives the time delay information of the paths, despreads the baseband signal, and combines despread signals.

Abstract: In the apparatus and method for separating carrier of multicarrier wireless communication receiver system, each carrier separation is performed after a quantization in a wireless communication receiver system such as a received multicarrier CDMA (Code Division Multiple Access) etc., to thereby reduce the whole number of quantizers and separate multicarrier from a received signal.

Abstract: A hybrid trace back apparatus and a high-speed Viterbi decoding system having the same are disclosed. The hybrid trace back apparatus includes: a register exchanging unit for receiving survivor values of each states from a path metric calculator, and obtaining a block survival value through a register exchange operation as much as a bit length for a block trace back operation; a first storing unit for the register exchange operation; a second storing unit for storing the block survival value obtained through the register exchange operation until the block survival value is written in a block trace back memory; and a block trace back unit for outputting decoded data by performing a block trace back operation while writing a value of the second storing unit.

Abstract: A Fast Fourier Transform (FFT) apparatus for selectively performing Fast Hadamard transform (FHT), and a complementary code keying (CCK) modulation/demodulation apparatus using the same are disclosed. In the present invention, OFDM module and CCK module are integrated as one module having lower complexity compared to conventional scheme by embodying the CCK modulation using FFT structure in the OFDM module, and embodying the suboptimal and the optimized CCK modulations using FFT structure in OFDM module. Furthermore, according to the present invention, CDMA, OFDM, CCK modules may be integrated as single module.

Abstract: Provided are a flexible bit rate code vector generation method and a wideband vocoder employing the same. This invention implements a flexible bit rate by getting three code vectors which are composed of 24, 16, and 8 pulses, at a time in a search process, through improvement of an algebraic codebook search process in a wideband AMR-WB vocoder. The method includes the steps of: performing a preprocess, wherein the preprocess divides a sub-frame by tracks and decides a pulse position having a maximum value in each track; among a plurality of pulses to be searched, fixing a same number of pulses as the tracks to the position with the maximum value of each track sequentially, and searching optimal positions having a minimum error with a target signal by combining two pulses in two consecutive tracks for the remaining pulses; and creating a code vector with flexible bit rate.

Abstract: A symbol combining method in a Rake receiver, which relates to a method for combining the demodulated multi-path signals in a demodulation process of a code division multiple access communication system. The symbol combining method, a Rake receiver using the symbol combining method and a method for driving the Rake receiver, remarkably reduce a hardware complexity of a FIFO register used to regulate a timing synchronization of each finger in Rake receiver by using a new algorithm in a combining process when a CDMA communication system combines a plurality of multi-path signals therebetween. Whereas a conventional combining algorithm uses an individual FIFO register every finger so as to adjust a timing synchronization of each symbol before combining a demodulated symbol, the inventive combining algorithm performs a symbol combining operation as well as a timing synchronization of a symbol at the same time, and performs a combining action by using only one FIFO register irrespective of the number of fingers.

Abstract: Disclosed is an apparatus for performing both FHT (Fast Hadamard Transform) and FFT (Fast Fourier Transform). This apparatus determines the phase coefficients as constantly “1” when performing the FHT, and changes the input order of input data to a reverse order of bits when performing the FFT. In addition, the apparatus, which can process a plurality of input data sets simultaneously, classifies the received signals into multi-path signals and multi-antenna signals, thus processing the multi-path signals separately from the multi-antenna signals, or directly processes multi-antenna signals.

Abstract: A finite impulse response filter of 1:4 interpolation with 108 taps for outputting filter output data of 8 bits with respect to filter input data of 4 bits includes four shifting and storing unit of 27 bits for unifying bits of filter input data of 4 bits, which is 2's complement to shift and store the bi-unified input data, first selection unit for selecting any one of the input data stored in the four shifting and storing unit of 27 bits, address generating unit for generating addresses of lookup tables corresponding to each of a plurality of filter coefficients groups, first to fourth lookup table groups for generating filter outputs of each filter coefficients group, four accumulating unit for shifting the filter outputs of the filter coefficients groups respectively outputted in parallel from the first to the fourth lookup table groups, and second selection unit for serially converting the outputs from each of the four accumulators in accordance with filter coefficients groups.

Abstract: An interleaving/deinterleaving processing method, a channel encoding system using it and a computer readable recording media for realizing it is provided.

Abstract: A region searcher, a method of driving the same, and a code searcher using the same are disclosed. When a predetermined region is iteratively searched, the energy value corresponding to the same hypothesis location value is stored by using a searcher having divided two buffers, thereby the implementation complexity thereof can be remarkably reduced, without using a simple memory.

Abstract: A multipath searching apparatus for searching a short-delay multipath in a spread spectrum communications system and a method thereof are provided.

Abstract: In the apparatus and method for separating carrier of multicarrier wireless communication receiver system, each carrier separation is performed after a quantization in a wireless communication receiver system such as a received multicarrier CDMA (Code Division Multiple Access) etc., to thereby reduce the whole number of quantizers and separate multicarrier from a received signal.

Abstract: A symbol combining method in a Rake receiver, which relates to a method for combining the demodulated multi-path signals in a demodulation process of a code division multiple access communication system. The symbol combining method, a Rake receiver using the symbol combining method and a method for driving the Rake receiver, remarkably reduce a hardware complexity of a FIFO register used to regulate a timing synchronization of each finger in Rake receiver by using a new algorithm in a combining process when a CDMA communication system combines a plurality of multi-path signals therebetween. Whereas a conventional combining algorithm uses an individual FIFO register every finger so as to adjust a timing synchronization of each symbol before combining a demodulated symbol, the inventive combining algorithm performs a symbol combining operation as well as a timing synchronization of a symbol at the same time, and performs a combining action by using only one FIFO register irrespective of the number of fingers.

Abstract: A finite impulse response filter of 1:4 interpolation with 108 taps for outputting filter output data of 8 bits with respect to filter input data of 4 bits includes four shifting and storing unit of 127 bits for unifying bits of filter input data of 4 bits, which is 2's complement to shift and store the bi-unified input data, first selection unit for selecting any one of the input data stored in the four shifting and storing unit of 27 bits, address generating unit for generating addresses of lookup tables corresponding to each of a plurality of filter coefficients groups, first to fourth lookup table groups for generating filter outputs of each filter coefficients group, four accumulating unit for shifting the filter outputs of the filter coefficients groups respectively outputted in parallel from the first to the fourth lookup table groups, and second selection unit for serially converting the outputs from each of the four accumulators in accordance with filter coefficients groups.

Abstract: An interleaving/deinterleaving processing method, a channel encoding system using it and a computer readable recording media for realizing it is provided.

Abstract: A hadamard code generation circuit is disclosed. The circuit includes a start reset signal generator for generating a start reset signal START.sub.-- RESET when a 6-bit output signal REF.sub.-- C from the 6-bit reference counter, a higher 4-bit index output signal H(5:2) of the 6-bit register and a 2-bit value from a ground circuit are identical; a "0" value force allocation unit for outputting a FORCE.sub.-- 0.sub.-- DEL signal for forcibly allocating all values of the 0th column to "0" when a 4-bit output signal REF.sub.-- C (5:2) from the 6-bit reference counter and a 4-bit value from the ground circuit are identical; a 2-bit counter for receiving the start reset signal and an external clock signal, outputting lowest bit signals C1 and C0 and outputting a carry-out signal; a 4-bit counter operated in accordance with a result that an inverted FORCE.sub.

Abstract: In case microcontroller and digital signal processing blocks are used together in one chip, there has been a problem in which the synchronization of the clocks are not consistent with each other when sending a signal from one block to another. In addition, when a reference clock is activated during a change of input signal, an incomplete interval has occurred. Accordingly, in order to solve the above mentioned problem, the present invention discloses a synchronizing circuit which uses a latch circuit("RS") consisted of NAND gates to synchronize an asynchronous input data and a reference clock, thereby solving the problem in which an incomplete interval occurs.

Abstract: A mobile communication method is disclosed, and particularly a power of two length pseudorandom noise sequence generator is disclosed, in which a pseudorandom noise code sequence is generated to use it for a direct sequence spreading of communication signals in a spread spectrum communication system. In the PN sequence generator, a mask value and a comparison value are calculated for shifting the PN sequence output having a length of 2.sup.N as much as wanted, so that the PN sequence can be shifted as much as a predetermined value in response to the single clock signal. In order to generate a PN sequence of the desired timing, a new PN mask value is directly obtained from the current PN mask value and the offset shift value to be shifted, and at the same time, a comparison value corresponding to the mask value is obtained, whereby ultimately a PN sequence having a length of 2.sup.N after shifting the cycle as much as the desired shifting value is obtained.