Abstract: Provided are a precursor supply unit, a substrate processing system, and a method of fabricating a semiconductor device using the same. The precursor supply unit may include an outer container, an inner container provided in the outer container and used to store a precursor source, a gas injection line having an injection port, which is provided below the inner container and in the outer container and is used to provide a carrier gas into the outer container, and a gas exhaust line having an exhaust port, which is provided below the inner container and in the outer container and is used to exhaust the carrier gas in the outer container and a precursor produced from the precursor source.

Abstract: Disclosed are a refrigerator and a method for displaying a user interface on the refrigerator, a user terminal, and a method for performing a function in the user terminal. The refrigerator according to the present disclosure may include: a storage chamber storing food therein; a temperature detection unit configured to detect the internal temperature of the storage chamber; a cooling unit configured to supply cold air to the storage chamber; a camera configured to photograph food in the storage chamber; a communication unit configured to communicate with a user terminal; a display; at least one processor electrically connected to the temperature detection unit, the camera, the cooling unit, and the communication unit; and a memory electrically connected to the at least one processor.

Abstract: A semiconductor memory device and associated methods, the device including first and second lower conductive lines extending in a first direction; a first middle conductive line on the first and second lower conductive lines and extending in a second direction; first and second memory cells between the first and second lower conductive lines and the first middle conductive line; an air gap support layer between the first and second memory cells; and a first air gap between the first and second memory cells and under the air gap support layer, wherein an upper surface of the air gap support layer lies in a same plane as the first and second memory cells, the first and second memory cells include first and second OTS layers and first and second phase-change layers, and the first air gap overlaps the first and second phase-change layers.

Abstract: The present disclosure provides a flexible circuit board for multiple signal transmission including a first dielectric layer; a plurality of first side grounds formed on one surface of the first dielectric layer to be parallel; first signal lines formed between the plurality of first side grounds; and a plurality of through holes which is formed in each of the plurality of first side grounds with an interval, along a length direction of the first side grounds.

Abstract: The present invention provides a flexible printed circuit board comprising: a first power line formed on one surface of a first dielectric layer; and a second power line formed on one surface of a second dielectric layer spaced apart from the first dielectric layer on a bottom surface of the first dielectric layer. There is an overlapping area in which the first power line and the second power line overlap, the first power line and the second power line are connected at a first end of the overlapping area through a via hole, and the first power line and the second power line are connected at a second end of the overlapping area through another via hole.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the device including a substrate; a lower structure including pad patterns on the substrate, upper surfaces of the pad patterns being at an outer side of the lower structure; a plurality of lower electrodes contacting the upper surfaces of the pad patterns; a dielectric layer and an upper electrode sequentially stacked on a surface of each of the lower electrodes; and a hydrogen supply layer including hydrogen, the hydrogen supply layer being between the lower electrodes and closer to the substrate than the dielectric layer is to the substrate.

Abstract: A semiconductor device includes first and second active patterns each extending in a first direction and are spaced apart from each other in a second direction that is perpendicular to the first direction. A field insulating layer is disposed between the first active pattern and the second active pattern. A first gate structure is disposed on the first active pattern and extends in the second direction. An interlayer insulating layer is disposed between the first gate structure and the field insulating layer. The interlayer insulating layer includes a first part disposed below the first gate structure. A spacer is disposed between the first gate structure and the first part of the interlayer insulating layer.

Abstract: A semiconductor device includes a lower electrode on a substrate, a capacitor dielectric film extending on the lower electrode along a side surface of the lower electrode that is perpendicular to the substrate, an upper electrode on the capacitor dielectric film, an interface layer including a hydrogen blocking film and a hydrogen bypass film on the upper electrode, the hydrogen blocking film including a conductive material, and a contact plug penetrating the interface layer and electrically connected to the upper electrode.

Abstract: A method of manufacturing a vertical memory device includes forming a first sacrificial layer on a substrate, the first sacrificial layer including a first insulating material, forming a mold including an insulation layer and a second sacrificial layer alternately and repeatedly stacked on the first sacrificial layer, the insulation layer and the second sacrificial layer including second and third insulating materials, respectively, different from the first insulating material, forming a channel through the mold and the first sacrificial layer, forming an opening through the mold and the first sacrificial layer to expose an upper surface of the substrate, removing the first sacrificial layer through the opening to form a first gap, forming a channel connecting pattern to fill the first gap, and replacing the second sacrificial layer with a gate electrode.

Abstract: The present invention provides a temperature sensitive hydrogel composition including a nucleic acid and chitosan. Since the hydrogel has excellent biocompatibility and biostability, and simultaneously has sol-gel phase transition properties depending on temperature changes, the hydrogel is present in a sol state at room temperature and becomes a gel when the hydrogel is injected into the human body or applied on the surface of epithelial skin and the temperature increases. Thus, the temperature-sensitive hydrogel of the present invention can be directly injected into and applied on certain parts requiring treatment and the retention and attaching time of a drug is increased through gelation depending on the temperature so that drug efficacy is sufficiently exhibited. Therefore, it is expected that the temperature-sensitive hydrogel of the present invention can be utilized for various treatments.

Abstract: A semiconductor device including a substrate that includes a cell array region and a peripheral circuit region; a cell transistor on the cell array region of the substrate; a peripheral transistor on the peripheral circuit region of the substrate; a first interconnection layer connected to the cell transistor; a second interconnection layer connected to the peripheral transistor; an interlayer dielectric layer covering the first interconnection layer; and a blocking layer spaced apart from the first interconnection layer, the blocking layer covering a top surface and a sidewall of the second interconnection layer.

Abstract: A semiconductor memory device includes a cell substrate, a mold structure including a plurality of gate electrodes stacked on the cell substrate, the gate electrodes including a first ground selection line, a second ground selection line and a plurality of word lines, which are sequentially stacked, a channel structure that extends in a vertical direction that crosses an upper surface of the cell substrate and penetrates the mold structure, a partial isolation region that extends in a first direction that is parallel with the upper surface of the cell substrate and partially separates the mold structure, and a ground isolation structure that connects two partial isolation regions adjacent to each other in the first direction, extends in the vertical direction and penetrates the first ground selection line and the second ground selection line, wherein a width of the ground isolation structure increases with distance from the cell substrate.

Abstract: A semiconductor device including a substrate that includes a cell array region and a peripheral circuit region; a cell transistor on the cell array region of the substrate; a peripheral transistor on the peripheral circuit region of the substrate; a first interconnection layer connected to the cell transistor; a second interconnection layer connected to the peripheral transistor; an interlayer dielectric layer covering the first interconnection layer; and a blocking layer spaced apart from the first interconnection layer, the blocking layer covering a top surface and a sidewall of the second interconnection layer.

Abstract: An antenna carrier includes a flexible circuit board, the flexible circuit board comprising: a first dielectric formed to include a width direction and a length direction; a first signal line positioned on one side in the width direction of an upper surface or a lower surface of the first dielectric; a second signal line spaced apart from the first signal line to the other side in the width direction and positioned on the upper surface or the lower surface of the first dielectric; a second dielectric positioned on one side in the width direction above the first dielectric and having the first signal line positioned below the second dielectric; a third dielectric spaced apart from the second dielectric to the other side in the width direction and positioned below the first dielectric, and having the second signal line positioned above the third dielectric; a first ground; and a second ground.

Abstract: A semiconductor device includes a first active pattern disposed on a substrate, a device isolation layer filling a trench that defines the first active pattern, a first channel pattern and a first source/drain pattern disposed on the first active pattern in which the first channel pattern includes semiconductor patterns stacked and spaced apart from each other, a gate electrode that extends and runs across the first channel pattern, a gate dielectric layer disposed between the first channel pattern and the gate electrode, and a first passivation pattern disposed between the device isolation layer and a first sidewall of the first active pattern. The first passivation pattern includes an upper part that protrudes upwardly from the device isolation layer, and a lower part buried in the device isolation layer. The gate dielectric layer covers the upper part of the first passivation pattern.

Abstract: The present disclosure provides a flexible circuit board for multiple signal transmission including a first dielectric layer; a plurality of first side grounds formed on one surface of the first dielectric layer to be parallel; first signal lines formed between the plurality of first side grounds; and a plurality of through holes which is formed in each of the plurality of first side grounds with an interval, along a length direction of the first side grounds.

Abstract: In a method of manufacturing a vertical memory device, a first sacrificial layer including a nitride is formed on a substrate. A mold including an insulation layer and a second sacrificial layer alternately and repeatedly stacked on the first sacrificial layer is formed. The insulation layer and the second sacrificial layer include a first oxide and a second oxide, respectively. A channel is formed through the mold and the first sacrificial layer. An opening is formed through the mold and the first sacrificial layer to expose an upper surface of the substrate. The first sacrificial layer is removed through the opening to form a first gap. A channel connecting pattern is formed to fill the first gap. The second sacrificial layer is replaced with a gate electrode.

Abstract: A flexible circuit board comprises: a first dielectric which has a first signal line in contact with an upper surface or lower surface thereof, has a greater width than the first signal line, and extends along an extension direction of the first signal line; a second dielectric which is located below the first dielectric, has a second signal line in contact with the upper or lower surface thereof, has a greater width than the second signal line, and extends along an extension direction of the second signal line; a vertical section in which the first signal line and the second signal line are located on a same vertical line and the first signal line and the second signal line extend in parallel; and a horizontal section in which the position of the first signal line or the second signal line is changed through a via hole.

Abstract: A semiconductor manufacturing apparatus includes a chamber that includes a station in which a substrate is provided, a substrate holder that is in the station and receives the substrate, and lower showerheads below the substrate holder, the lower showerheads including an isotropic showerhead having first nozzle holes that isotropically provide a first reaction gas on a bottom surface of the substrate, and a striped showerhead having striped nozzle regions and striped blank regions between the striped nozzle regions, the striped nozzle regions having second nozzle holes that non-isotropically provide a second reaction gas on the bottom surface of the substrate.

Abstract: A semiconductor memory device and associated methods, the device including first and second lower conductive lines extending in a first direction; a first middle conductive line on the first and second lower conductive lines and extending in a second direction; first and second memory cells between the first and second lower conductive lines and the first middle conductive line; an air gap support layer between the first and second memory cells; and a first air gap between the first and second memory cells and under the air gap support layer, wherein an upper surface of the air gap support layer lies in a same plane as the first and second memory cells, the first and second memory cells include first and second OTS layers and first and second phase-change layers, and the first air gap overlaps the first and second phase-change layers.