Patents by Inventor Ikenna Odinaka
Ikenna Odinaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11757452Abstract: A class of complex logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. At least one input to an individual multi-input majority gate is a fixed input. Other inputs are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node, which provides a majority function of the inputs. The summing node is coupled to a CMOS logic. Leakage through the capacitors is configured such that capacitors of a majority gate have substantially equal leakage, and this leakage has a I-V behavior which is symmetric. As such, reset device(s) on the summing node are not used. The non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels, which reduces the high leakage problem faced from majority gates that use linear input capacitors.Type: GrantFiled: April 20, 2022Date of Patent: September 12, 2023Assignee: KEPLER COMPUTING INC.Inventors: Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Darshak Doshi, Rajeev Kumar Dokania, Sasikanth Manipatruni
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Patent number: 11750197Abstract: A class of complex logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. At least one input to an individual multi-input majority gate is a fixed input. Other inputs are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node, which provides a majority function of the inputs. The summing node is coupled to a CMOS logic. Leakage through the capacitors is configured such that capacitors of a majority gate have substantially equal leakage, and this leakage has a I-V behavior which is symmetric. As such, reset device(s) on the summing node are not used. The non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels, which reduces the high leakage problem faced from majority gates that use linear input capacitors.Type: GrantFiled: April 20, 2022Date of Patent: September 5, 2023Assignee: KEPLER COMPUTING INC.Inventors: Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Darshak Doshi, Rajeev Kumar Dokania, Sasikanth Manipatruni
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Patent number: 11748537Abstract: A computer-aided design (CAD) tool is provided for logic optimization and synthesis. The CAD tool executes a process that involves optimizing power, performance, and area (PPA) of a logic circuit by minimizing a number of CMOS gates, and majority and/or minority gates in the circuit and its depth. The CAD tool implements a methodology of optimizing logic synthesis based on a mix of standard cell libraries (such as AND, OR, NAND, NOR, XOR, Multiplexer, full adder, half adder, etc.) and varying input majority and minority gates (where the number of inputs in the minority and majority gates could vary as odd numbers from 3 and above). The standard cell libraries cells may contain minority and/or majority gates.Type: GrantFiled: July 23, 2021Date of Patent: September 5, 2023Inventors: Ikenna Odinaka, Sasikanth Manipatruni, Darshak Doshi, Rajeev Kumar Dokania, Amrita Mathuriya
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Patent number: 11742860Abstract: A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. Input signals in the form of digital signals are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node which provides a majority function of the inputs. The majority node is then coupled driver circuitry which can be any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. In the multi-input majority or minority gates, the non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels. Bringing the majority output close to rail-to-rail voltage eliminates the high leakage problem faced from majority gates formed using linear input capacitors.Type: GrantFiled: June 22, 2022Date of Patent: August 29, 2023Assignee: Kepler Computing Inc.Inventors: Sasikanth Manipatruni, Rafael Rios, Neal Reynolds, Ikenna Odinaka, Robert Menezes, Rajeev Kumar Dokania, Ramamoorthy Ramesh, Amrita Mathuriya
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Publication number: 20230251828Abstract: Asynchronous full-adder circuit is described. The full-adder includes majority and/or minority gates some of which receive two first inputs (A.t, A.f), two second inputs (B.t, B.f), two carry inputs (Cin.t, Cin.f), third acknowledgement input (Cout.e), and fourth acknowledgement input (Sum.e), and generate controls to control gates of transistors, wherein the transistors are coupled to generate two carry outputs (Cout.t, Cout.e), two sum outputs (Sum.t, Sum.e), first acknowledgement output (A.e), second acknowledgement output (B.e), and third acknowledgement output (Cin.e). The majority and/or minority gates comprise CMOS gates or multi-input capacitive circuitries. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the asynchronous full-adder circuit.Type: ApplicationFiled: February 7, 2022Publication date: August 10, 2023Applicant: Kepler Computing Inc.Inventors: Amrita Mathuriya, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni
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Patent number: 11721690Abstract: An apparatus and configuring scheme where a ferroelectric capacitive input circuit can be programmed to perform different logic functions by adjusting the switching threshold of the ferroelectric capacitive input circuit. Digital inputs are received by respective capacitors on first terminals of those capacitors. The second terminals of the capacitors are connected to a summing node. A pull-up and pull-down device are coupled to the summing node. The pull-up and pull-down devices are controlled separately. During a reset phase, the pull-up and pull-down devices are turned on in a sequence, and inputs to the capacitors are set to condition the voltage on node n1. As such, a threshold for the capacitive input circuit is set. After the reset phase, an evaluation phase follows. In the evaluation phase, the output of the capacitive input circuit is determined based on the inputs and the logic function configured during the reset phase.Type: GrantFiled: December 15, 2021Date of Patent: August 8, 2023Assignee: Kepler Computing Inc.Inventors: Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania, Sasikanth Manipatruni
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Patent number: 11716086Abstract: Asynchronous circuits implemented using threshold gate(s) and/or majority gate(s) (or minority gate(s)) are described. The new class of asynchronous circuits can operate at lower power supply levels (e.g., less than 1V on advanced technology nodes) because stack of devices between a supply node and ground are significantly reduced compared to traditional asynchronous circuits. The asynchronous circuits here result in area reduction (e.g., 3× reduction compared to traditional asynchronous circuits) and provide higher throughput/mm2 (e.g., 2× higher throughput compared to traditional asynchronous circuits). The threshold gate(s), majority/minority gate(s) can be implemented using capacitive input circuits. The capacitors can have linear dielectric or non-linear polar material as dielectric.Type: GrantFiled: December 23, 2021Date of Patent: August 1, 2023Assignee: Kepler Computing Inc.Inventors: Sasikanth Manipatruni, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Amrita Mathuriya
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Patent number: 11716084Abstract: Asynchronous circuits implemented using threshold gate(s) and/or majority gate(s) (or minority gate(s)) are described. The new class of asynchronous circuits can operate at lower power supply levels (e.g., less than 1V on advanced technology nodes) because stack of devices between a supply node and ground are significantly reduced compared to traditional asynchronous circuits. The asynchronous circuits here result in area reduction (e.g., 3× reduction compared to traditional asynchronous circuits) and provide higher throughput/mm2 (e.g., 2× higher throughput compared to traditional asynchronous circuits). The threshold gate(s), majority/minority gate(s) can be implemented using capacitive input circuits. The capacitors can have linear dielectric or non-linear polar material as dielectric.Type: GrantFiled: December 23, 2021Date of Patent: August 1, 2023Assignee: Kepler Computing Inc.Inventors: Sasikanth Manipatruni, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Amrita Mathuriya
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Patent number: 11716085Abstract: Asynchronous circuits implemented using threshold gate(s) and/or majority gate(s) (or minority gate(s)) are described. The new class of asynchronous circuits can operate at lower power supply levels (e.g., less than 1V on advanced technology nodes) because stack of devices between a supply node and ground are significantly reduced compared to traditional asynchronous circuits. The asynchronous circuits here result in area reduction (e.g., 3× reduction compared to traditional asynchronous circuits) and provide higher throughput/mm2 (e.g., 2× higher throughput compared to traditional asynchronous circuits). The threshold gate(s), majority/minority gate(s) can be implemented using capacitive input circuits. The capacitors can have linear dielectric or non-linear polar material as dielectric.Type: GrantFiled: December 23, 2021Date of Patent: August 1, 2023Assignee: Kepler Computing, Inc.Inventors: Sasikanth Manipatruni, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Amrita Mathuriya
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Patent number: 11716083Abstract: Asynchronous circuits implemented using threshold gate(s) and/or majority gate(s) (or minority gate(s)) are described. The new class of asynchronous circuits can operate at lower power supply levels (e.g., less than 1V on advanced technology nodes) because stack of devices between a supply node and ground are significantly reduced compared to traditional asynchronous circuits. The asynchronous circuits here result in area reduction (e.g., 3× reduction compared to traditional asynchronous circuits) and provide higher throughput/mm2 (e.g., 2× higher throughput compared to traditional asynchronous circuits). The threshold gate(s), majority/minority gate(s) can be implemented using capacitive input circuits. The capacitors can have linear dielectric or non-linear polar material as dielectric.Type: GrantFiled: December 23, 2021Date of Patent: August 1, 2023Assignee: Kepler Computing Inc.Inventors: Sasikanth Manipatruni, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Amrita Mathuriya
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Patent number: 11705905Abstract: An apparatus and configuring scheme where a ferroelectric capacitive input circuit can be programmed to perform different logic functions by adjusting the switching threshold of the ferroelectric capacitive input circuit. Digital inputs are received by respective capacitors on first terminals of those capacitors. The second terminals of the capacitors are connected to a summing node. A pull-up and pull-down device are coupled to the summing node. The pull-up and pull-down devices are controlled separately. During a reset phase, the pull-up and pull-down devices are turned on in a sequence, and inputs to the capacitors are set to condition the voltage on node n1. As such, a threshold for the capacitive input circuit is set. After the reset phase, an evaluation phase follows. In the evaluation phase, the output of the capacitive input circuit is determined based on the inputs and the logic function configured during the reset phase.Type: GrantFiled: December 14, 2021Date of Patent: July 18, 2023Assignee: Kepler Computing, Inc.Inventors: Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania, Sasikanth Manipatruni
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Patent number: 11705906Abstract: A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. Input signals in the form of digital signals are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node which provides a majority function of the inputs. In the multi-input majority or minority gates, the non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels. In some examples, the nodes of the non-linear input capacitors are conditioned once in a while to preserve function of the multi-input majority gates.Type: GrantFiled: May 21, 2021Date of Patent: July 18, 2023Assignee: Kepler Computing Inc.Inventors: Rajeev Kumar Dokania, Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Robert Menezes, Ramamoorthy Ramesh, Sasikanth Manipatruni
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Publication number: 20230223936Abstract: Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.Type: ApplicationFiled: January 14, 2022Publication date: July 13, 2023Applicant: Kepler Computing Inc.Inventors: Amrita Mathuriya, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni
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Patent number: 11699699Abstract: An apparatus and configuring scheme where a ferroelectric capacitive input circuit can be programmed to perform different logic functions by adjusting the switching threshold of the ferroelectric capacitive input circuit. Digital inputs are received by respective capacitors on first terminals of those capacitors. The second terminals of the capacitors are connected to a summing node. A pull-up and pull-down device are coupled to the summing node. The pull-up and pull-down devices are controlled separately. During a reset phase, the pull-up and pull-down devices are turned on in a sequence, and inputs to the capacitors are set to condition the voltage on node n1. As such, a threshold for the capacitive input circuit is set. After the reset phase, an evaluation phase follows. In the evaluation phase, the output of the capacitive input circuit is determined based on the inputs and the logic function configured during the reset phase.Type: GrantFiled: December 15, 2021Date of Patent: July 11, 2023Assignee: Kepler Computing, Inc.Inventors: Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania, Debo Olaosebikan, Sasikanth Manipatruni
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Patent number: 11688733Abstract: An apparatus and configuring scheme where a paraelectric capacitive input circuit can be programmed to perform different logic functions by adjusting the switching threshold of the paraelectric capacitive input circuit. Digital inputs are received by respective capacitors on first terminals of those capacitors. The second terminals of the capacitors are connected to a summing node. A pull-up and pull-down device are coupled to the summing node. The pull-up and pull-down devices are controlled separately. During a reset phase, the pull-up and/or pull-down devices are turned on or off in a sequence, and inputs to the capacitors are set to condition the voltage on node nl. As such, a threshold for the capacitive input circuit is set. After the reset phase, an evaluation phase follows. In the evaluation phase, the output of the capacitive input circuit is determined based on the inputs and the logic function configured during the reset phase.Type: GrantFiled: December 15, 2021Date of Patent: June 27, 2023Assignee: Kepler Computing Inc.Inventors: Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania, Sasikanth Manipatruni
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Patent number: 11664371Abstract: An apparatus and configuring scheme where a paraelectric capacitive input circuit can be programmed to perform different logic functions by adjusting the switching threshold of the paraelectric capacitive input circuit. Digital inputs are received by respective capacitors on first terminals of those capacitors. The second terminals of the capacitors are connected to a summing node. A pull-up and pull-down device are coupled to the summing node. The pull-up and pull-down devices are controlled separately. During a reset phase, the pull-up and/or pull-down devices are turned on or off in a sequence, and inputs to the capacitors are set to condition the voltage on node n1. As such, a threshold for the capacitive input circuit is set. After the reset phase, an evaluation phase follows. In the evaluation phase, the output of the capacitive input circuit is determined based on the inputs and the logic function configured during the reset phase.Type: GrantFiled: December 15, 2021Date of Patent: May 30, 2023Assignee: Kepler Computing Inc.Inventors: Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania, Debo Olaosebikan, Sasikanth Manipatruni
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Patent number: 11664370Abstract: An apparatus and configuring scheme where a paraelectric capacitive input circuit can be programmed to perform different logic functions by adjusting the switching threshold of the paraelectric capacitive input circuit. Digital inputs are received by respective capacitors on first terminals of those capacitors. The second terminals of the capacitors are connected to a summing node. A pull-up and pull-down device are coupled to the summing node. The pull-up and pull-down devices are controlled separately. During a reset phase, the pull-up and/or pull-down devices are turned on or off in a sequence, and inputs to the capacitors are set to condition the voltage on node n1. As such, a threshold for the capacitive input circuit is set. After the reset phase, an evaluation phase follows. In the evaluation phase, the output of the capacitive input circuit is determined based on the inputs and the logic function configured during the reset phase.Type: GrantFiled: December 14, 2021Date of Patent: May 30, 2023Assignee: Kepler Corpating inc.Inventors: Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania, Sasikanth Manipatruni
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Patent number: 11658664Abstract: Asynchronous circuits implemented using threshold gate(s) and/or majority gate(s) (or minority gate(s)) are described. The new class of asynchronous circuits can operate at lower power supply levels (e.g., less than 1V on advanced technology nodes) because stack of devices between a supply node and ground are significantly reduced compared to traditional asynchronous circuits. The asynchronous circuits here result in area reduction (e.g., 3× reduction compared to traditional asynchronous circuits) and provide higher throughput/mm2 (e.g., 2× higher throughput compared to traditional asynchronous circuits). The threshold gate(s), majority/minority gate(s) can be implemented using capacitive input circuits. The capacitors can have linear dielectric or non-linear polar material as dielectric.Type: GrantFiled: December 23, 2021Date of Patent: May 23, 2023Assignee: Kepler Computing Inc.Inventors: Sasikanth Manipatruni, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Amrita Mathuriya
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Patent number: 11652487Abstract: Asynchronous circuits implemented using threshold gate(s) and/or majority gate(s) (or minority gate(s)) are described. The new class of asynchronous circuits can operate at lower power supply levels (e.g., less than 1V on advanced technology nodes) because stack of devices between a supply node and ground are significantly reduced compared to traditional asynchronous circuits. The asynchronous circuits here result in area reduction (e.g., 3× reduction compared to traditional asynchronous circuits) and provide higher throughput/mm2 (e.g., 2× higher throughput compared to traditional asynchronous circuits). The threshold gate(s), majority/minority gate(s) can be implemented using capacitive input circuits. The capacitors can have linear dielectric or non-linear polar material as dielectric.Type: GrantFiled: December 23, 2021Date of Patent: May 16, 2023Assignee: Kepler Computing Inc.Inventors: Sasikanth Manipatruni, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Amrita Mathuriya
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Patent number: 11652482Abstract: Asynchronous circuits implemented using threshold gate(s) and/or majority gate(s) (or minority gate(s)) are described. The new class of asynchronous circuits can operate at lower power supply levels (e.g., less than 1V on advanced technology nodes) because stack of devices between a supply node and ground are significantly reduced compared to traditional asynchronous circuits. The asynchronous circuits here result in area reduction (e.g., 3× reduction compared to traditional asynchronous circuits) and provide higher throughput/mm2 (e.g., 2× higher throughput compared to traditional asynchronous circuits). The threshold gate(s), majority/minority gate(s) can be implemented using capacitive input circuits. The capacitors can have linear dielectric or non-linear polar material as dielectric.Type: GrantFiled: December 23, 2021Date of Patent: May 16, 2023Assignee: Kepler Computing Inc.Inventors: Sasikanth Manipatruni, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Amrita Mathuriya