Patents by Inventor Ikuhiro Yamamura

Ikuhiro Yamamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100136738
    Abstract: To arrange diffusion-inhibitory films 5a, 5b, and 5c for inhibiting the diffusion of a wiring material absent in a region on or above a light receiving unit 2,the diffusion-inhibitory films 5a, 5b, and 5c formed on a region above the light receiving unit 2 are selectively removed. Alternatively, the diffusion-inhibitory films are arranged only on top surfaces of wirings 4a, 4b, and 4c, and only a passivation film 12 and interlayer insulating films 3a, 3b, and 3c are arranged in the region on or above the light receiving unit 2. Thus, with less interface between different insulation films and less reflection of incident light in an incident region, the incident light 13 highly efficiently passes through these insulating films and comes into the light receiving unit 2. The light receiving unit 2 can thereby receive a sufficient quantity of the incident light 13.
    Type: Application
    Filed: February 9, 2010
    Publication date: June 3, 2010
    Applicant: Sony Corporation
    Inventor: Ikuhiro Yamamura
  • Patent number: 7474583
    Abstract: A semiconductor memory device has SRAM cells each including: a pair of inverters; a feed control switch connected between a feeding point of the pair of inverters and a power supply voltage supply line; and a boosting device configured to boost a voltage of the feeding point electrically isolated from the power supply voltage supply line by the feed control switch.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: January 6, 2009
    Assignee: Sony Corporation
    Inventor: Ikuhiro Yamamura
  • Patent number: 7465965
    Abstract: A semiconductor device including: a bulk semiconductor substrate; an access transistor; a thruster formed on the bulk semiconductor substrate connecting to the access transistor; an element separating region to separate the region for the access transistor and the region for the thruster from each other; and a wiring layer connecting one of the diffused layers of the access transistor and the cathode of the thruster together through a connecting hole, the impurity region at the anode side of the thruster being composed of a p-type impurity region, an n-type impurity region, p-type impurity region, and an n-type impurity region, which are formed sequentially in the depth wise direction, with the lowermost n-type impurity region receiving the same voltage as that applied to the anode at the time of data holding.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: December 16, 2008
    Assignee: Sony Corporation
    Inventor: Ikuhiro Yamamura
  • Publication number: 20070127298
    Abstract: A semiconductor memory device has SRAM cells each including: a pair of inverters; a feed control switch connected between a feeding point of the pair of inverters and a power supply voltage supply line; and a boosting device configured to boost a voltage of the feeding point electrically isolated from the power supply voltage supply line by the feed control switch.
    Type: Application
    Filed: December 27, 2006
    Publication date: June 7, 2007
    Applicant: Sony Corporation
    Inventor: Ikuhiro Yamamura
  • Publication number: 20070075343
    Abstract: To arrange diffusion-inhibitory films 5a, 5b, and 5c for inhibiting the diffusion of a wiring material absent in a region on or above a light receiving unit 2, the diffusion-inhibitory films 5a, 5b, and 5c formed on a region above the light receiving unit 2 are selectively removed. Alternatively, the diffusion-inhibitory films are arranged only on top surfaces of wirings 4a, 4b, and 4c, and only a passivation film 12 and interlayer insulating films 3a, 3b, and 3c are arranged in the region on or above the light receiving unit 2. Thus, with less interface between different insulation films and less reflection of incident light in an incident region, the incident light 13 highly efficiently passes through these insulating films and comes into the light receiving unit 2. The light receiving unit 2 can thereby receive a sufficient quantity of the incident light 13.
    Type: Application
    Filed: November 30, 2006
    Publication date: April 5, 2007
    Inventor: Ikuhiro Yamamura
  • Patent number: 7196365
    Abstract: To arrange diffusion-inhibitory films 5a, 5b, and 5c for inhibiting the diffusion of a wiring material absent in a region on or above a light receiving unit 2, the diffusion-inhibitory films 5a, 5b, and 5c formed on a region above the light receiving unit 2 are selectively removed. Alternatively, the diffusion-inhibitory films are arranged only on top surfaces of wirings 4a, 4b, and 4c, and only a passivation film 12 and interlayer insulating films 3a, 3b, and 3c are arranged in the region on or above the light receiving unit 2. Thus, with less interface between different insulation films and less reflection of incident light in an incident region, the incident light 13 highly efficiently passes through these insulating films and comes into the light receiving unit 2. The light receiving unit 2 can thereby receive a sufficient quantity of the incident light 13.
    Type: Grant
    Filed: April 25, 2003
    Date of Patent: March 27, 2007
    Assignee: Sony Corporation
    Inventor: Ikuhiro Yamamura
  • Publication number: 20070051973
    Abstract: A semiconductor device including: a bulk semiconductor substrate; an access transistor; a thyristor formed on the bulk semiconductor substrate connecting to the access transistor; an element separating region to separate the region for the access transistor and the region for the thyristor from each other; and a wiring layer connecting one of the diffused layers of the access transistor and the cathode of the thyristor together through a connecting hole, the impurity region at the anode side of the thyristor being composed of a p-type impurity region, an n-type impurity region, p-type impurity region, and an n-type impurity region, which are formed sequentially in the depthwise direction, with the lowermost n-type impurity region receiving the same voltage as that applied to the anode at the time of data holding.
    Type: Application
    Filed: August 30, 2006
    Publication date: March 8, 2007
    Applicant: Sony Corporation
    Inventor: Ikuhiro Yamamura
  • Publication number: 20040000669
    Abstract: To arrange diffusion-inhibitory films 5a, 5b, and 5c for inhibiting the diffusion of a wiring material absent in a region on or above a light receiving unit 2, the diffusion-inhibitory films 5a, 5b, and 5c formed on a region above the light receiving unit 2 are selectively removed. Alternatively, the diffusion-inhibitory films are arranged only on top surfaces of wirings 4a, 4b, and 4c, and only a passivation film 12 and interlayer insulating films 3a, 3b, and 3c are arranged in the region on or above the light receiving unit 2. Thus, with less interface between different insulation films and less reflection of incident light in an incident region, the incident light 13 highly efficiently passes through these insulating films and comes into the light receiving unit 2. The light receiving unit 2 can thereby receive a sufficient quantity of the incident light 13.
    Type: Application
    Filed: April 25, 2003
    Publication date: January 1, 2004
    Inventor: Ikuhiro Yamamura
  • Publication number: 20030054622
    Abstract: A method of fabricating a semiconductor device is advantageous in preventing occurrence of an erroneous short-circuit and a withstand voltage failure in a connection hole and preventing occurrence of a failure at the time of burying a connection hole with a metal. A silicon carbo-nitride film is formed on a conductor or an interconnection of a Damascene structure formed on a silicon substrate (S1), the silicon carbo-nitride film is taken as a side wall or an interlayer insulating film (S2), a silicon oxide film is formed on the silicon carbo-nitride film (S3), the upper side silicon oxide film is etched using the lower side silicon carbo-nitride film as an etching stopper layer (S4), and a connection hole is formed (S5).
    Type: Application
    Filed: October 8, 2002
    Publication date: March 20, 2003
    Inventor: Ikuhiro Yamamura
  • Patent number: 6403421
    Abstract: A semiconductor nonvolatile memory device using SA-STI cells improved in quality and suitable for increasing the degree of integration is provided with a semiconductor substrate having in its surface a channel formation region; an element isolation insulating film buried in a trench formed in the semiconductor substrate so as to divide the channel formation region into a plurality of regions; a gate insulating film formed on the channel formation region; a floating gate provided with a first floating gate formed at an upper layer of the gate insulating film and second floating gates formed at facing sides of the same; an inter-layer insulating film formed at an upper layer of the first floating gate and the second floating gates; a control gate formed at an upper layer of the inter-layer insulating film; and a source-drain region former connected to the channel formation region.
    Type: Grant
    Filed: May 31, 2000
    Date of Patent: June 11, 2002
    Assignee: Sony Corporation
    Inventors: Naoshi Ikeda, Ikuhiro Yamamura, Hidetoshi Yamanaka