Abstract: A high speed test fixture for testing printed circuit board (PCB)-mounted high speed pin grid array (PGA) chips attaches to the solder side (underside) of the PCB to eliminate the need for lead-lengthening adapter sockets. As a result, the testing can be conducted at the actual chip operating speed with reduced noise, rather than at slower speeds required by "noisy" prior art approaches.

Abstract: A means of converting low voltage CMOS logic levels operating with a 3.3 volts logic level to low voltage PECL logic levels operating with a 3.3 volts supply voltage and a 0.8 volts logic level. The circuit design is process insensitive, and the characteristics of the converter emulate the emitter follower outputs of ECL devices. The converter solves the signal ringing problems caused by open output conditions, and is less susceptible to electromagnetic interference.

Abstract: A memory packaging scheme for high speed computer systems includes, several memory module sockets mounted to a printed circuit board and interconnected by a common set of address, data and control transmission lines within the printed circuit board. The transmission lines are interrupted at each connector. Cooperating memory modules, such as SIMM memory modules are installed in sequence into one or more of the module sockets in accordance with the requirements of the computer system. Installation of a memory module into a memory socket closes the open circuits for each one of the transmission lines at the memory socket, extending the uninterrupted length of the transmission lines to the next memory socket in the sequence.

Abstract: An apparatus for containing and cooling an integrated circuit device includes a container defining a chamber. The apparatus further includes a conduit positioned in the chamber and having an inner surface and an outer surface, the integrated circuit device being positionable in the chamber and securable to the outer surface of the conduit. In addition, the apparatus includes an insulating member positioned to provide thermal isolation between the container and the conduit.

Abstract: An apparatus for containing and cooling an integrated circuit device includes a container defining a chamber, a first portion of the container includes a first heat sink. The apparatus further includes a second heat sink positioned within the chamber, the integrated circuit device being securable to the second heat sink. Moreover, the apparatus includes a cooling device interposed between the first heat sink and the second heat sink. In addition, the apparatus includes an insulator positioned in the chamber so as to provide thermal isolation between a second portion of the container and the cooling device.

Abstract: A high speed computer data transfer system includes a transistor diode clamping circuit for limiting pre-charge voltages in the case where multiple pre-charge cycles occur before a pull-down operation. Data bus voltage swings between logic high and logic low levels as well as pull-down times are reduced, thus lowering the time needed to transfer the data. Also, body effect upon the clamping circuit is lowered. The preferred embodiment is implemented using complementary metal-oxide-semiconductor (CMOS) technology.

Abstract: A CMOS circuit having an input threshold, the CMOS circuit including a first field-effect transistor having a source connected to a first power supply terminal, a drain connected to an output terminal, a gate connected to an input terminal, and a first channel between the source and the drain having a first width and a first length. A programmable field-effect transistor circuit has a gate terminal connected to the input terminal, a drain terminal connected to the output terminal, a source terminal connected to a second power supply terminal, and a second channel circuit between the drain terminal and the source terminal having an effective width and an effective length. Programmable input terminals are connected to the second channel circuit for changing the ratio of the product of the first width times the effective length to the product of the effective width times the first length such that the input threshold voltage of the CMOS circuit is changed responsive to the change of the ratio.

Abstract: In a high speed digital computer data transfer system, data bus voltage swings between logic high and logic low levels are reduced by defining minimum and maximum bus voltages which lie between said logic levels, thus lowering bus transition and hence data transfer times. The output voltages are converted to the proper logic levels with the aid of a differential (sense) amplifier. The preferred embodiment is implemented using complementary metal-oxide-semiconductor (CMOS) technology.

Abstract: In a high speed complementary metal-oxide-semiconductor (CMOS) inter-integrated circuit (IC) chip communication system, transmission line voltage swings between logic high and logic low levels are reduced by defining minimum and maximum bus voltages which lie between CMOS logic levels, thus lowering bus transition and hence data transfer times. The system is versatile, and does not involve typical emitter-coupled logic (ECL) logic levels. Transceivers interfacing between IC chips and the backpanel transmit data in the reduced logic level range on a pre-charged transmission line, and receive and convert data back to CMOS levels. A limiting transistor in the transmitter portion of the transceiver limits logic low level of the transmission line. The receiver portion of the transceiver converts the voltages received to CMOS levels with the aid of a differential (sense) amplifier.

Abstract: A high speed computer data transfer system includes a clamping circuit for limiting pre-charge voltages in the case where multiple pre-charge cycles occur before a pull-down operation. Data bus voltage swings between logic high and logic low levels as well as pull-down times are reduced, thus lowering the time needed to transfer the data. The preferred embodiment is implemented using complementary metal-oxide-semiconductor (CMOS) technology.

Abstract: An emitter coupled logic (ECL)-to-complementary metal-oxide-semiconductor (CMOS) logic level translator is temperature compensated to track temperature induced shifts in the ECL logic levels. The translator includes a differential amplifier with mid-range reference voltage. A reference voltage generator supplies the reference voltage to the differential amplifier and has a temperature sensitive transistor which changes the value of the circuit output (reference) voltage ambient with temperature shifts.

Abstract: A pin grid array package for carrying an integrated circuit chip having input/output leads. The pin grid array package includes a carrier having a centrally located opening for carrying the integrated circuit chip, a plurality of input/output pins spaced around the periphery of the centrally located opening, interconnect leads on the carrier for connecting selected ones of the input/output pins to selected leads of the integrated circuit chip, and heat sink material around the periphery of the input/output pins which serves as a cooling-fin for efficient integrated circuit chip heat removal. Each of the plurality of input/output pins is normal to the plane of the integrated circuit chip and extends through the carrier with a first portion extending away from a first side of the carrier and a second portion extending away from a second side of the carrier.

Abstract: A data transmission system for transferring data signals between first and second buses is disclosed. The system includes means attached to the buses for the transfer of data signals to the buses and supply means connected to the buses for precharging the buses to a first voltage level. The system also includes circuit means connecting the buses and responsive to a data signal at a second voltage level on either of said buses for transferring the signal to the other bus.

Abstract: A three input Exclusive OR-NOR gate circuit. The circuit comprises inverters for receiving three input signals and for providing three inverted input signals, a power potential terminal, a reference potential terminal, and an Exclusive NOR output node and an Exclusive OR output node. The circuit also includes transistors of a first conductivity type responsive to the signals on the output nodes for connecting the power potential terminal solely to one of the output nodes, and transistors of a second conductivity type responsive to the input and inverted input signals for connecting the reference potential terminal solely to the other of the output nodes.

Abstract: The subject invention is an ECL to CMOS converter for converting high or low ECL logic signals. The converter comprises a CMOS inverter for providing low or high CMOS logic signals at its output in response to a first or second signal, respectively, applied to its input. The first signal must exceed a first predetermined value and the second signal must fall below a second predetermined value. The first and second predetermined values are such that either the low ECL signal does not fall below the second predetermined value or the high ECL signal does not exceed the first predetermined value. The converter also provides means for converting the high and low logic signals to the first and second signals, respectively.

Abstract: A MOS circuit for trimming a digital pulse signal by delaying the rising edge of the pulse signal for a predetermined period of time and passing the falling edge without delay. The circuit includes two MOS output transistors and a signal buffer. The signal buffer has a number of stages for delaying the pulse signal, with the number chosen to control the delay in the rising edge of the pulse signal. One of the output transistors receives the pulse signal at its drain and is enabled by the delayed pulse signal from the signal buffer to pass the pulse signal after the predetermined period of time to its source at the output of the circuit, so that the rising edge is delayed, but the falling edge is not. The other output transistor is enabled to ground the output of the circuit after the falling edge of the pulse signal. A self-booting circuit drives the gate of the one output transistor to assure that the voltage level of the trimmed signal will not be reduced by dissipation across the transistor.

Abstract: A double walled vessel having a styrofoam filling between the double walls internally supports a semiconductor circuit to which is attached at least one flat ribbon cable. The semiconductor circuit is immersed in liquid nitrogen with at least one flat ribbon cable extending to the top lip of the vessel. Carbon conductors are connected to each conductor of the flat ribbon cable and extend to the outer wall of the vessel. Another flat ribbon cable is connected to the carbon conductors and to an electrical connector. A double walled top having a styrofoam filling is secured to the vessel such that the carbon conductors are sealed between the styrofoam filling of the top and the double walled vessel thereby preventing the formation of frost on the flat ribbon cable and connector that is external to the sealed vessel. Various tubings are inserted through the double walled vessel to permit the insertion of liquid nitrogen and the drawing off of gaseous nitrogen.

Abstract: An ECL to CMOS converter which connects the ECL input signal directly to the source electrode of a MOS gate, and the gate electrode of the MOS gate is independently regulated by connection to a reference voltage that is current sinked through a D.C. path to the negative CMOS voltage supply terminal. The drain electrode of the MOS gate is connected to the input of a CMOS inverter to provide the necessary logic level shift. Another MOS gate provides a D.C. signal path by connecting the input of the CMOS inverter to the negative CMOS voltage supply terminal.

Abstract: The present invention is an Exclusive-OR circuit which uses a minimum number of components and which is particularly adapted for use as a building block for a parity checking circuit. The circuit only uses CMOS gates to reduce the number of included transistors.

Abstract: Apparatus and method for removably mounting an integrated circuit package having a plurality of electrical pins wherein a plurality of mating pins each having a receptacle filled with liquid mercury are connected to the electrical pins of the integrated circuit package and the temperature reduced such that the liquid mercury solidifies thereby firmly bonding the electrical pins together. The assembly may be inserted into a Dewar type vessel and covered with a low temperature liquified gas for the dual purpose of solidfying the liquid mercury and cooling the integrated circuit package.