Abstract: A terminator for a transceiver device for transmitting data signals to and receiving data signals from a second transceiver device over a transmission line therebetween. The terminator has a transmitter connected to the transmission line for transmitting data signals to the second transceiver device, a receiver connected to the transmission line for receiving data signals from the second transceiver device, a termination resistor connected to the transmission line for improving the transmission characteristics of the transmission line, and a switch device between the termination resistor and the transmission line. The switch device is closed for a portion of the time when the receiver is receiving data signals from the second transceiver device such that when it is closed the termination resistor is connected to the transmission line, and is open for the remainder to the time such that when it is open the termination resistor is not connected to the transmission line.

Abstract: The circuit of the present invention converts CMOS logic level signals to corresponding ECL logic level signals to permit the coupling of CMOS and ECL devices. In addition, the present invention maintains a relatively constant impedance as the logic levels on its output change. The circuit has an input terminal connectable to a source of a first set of logic signals and an output terminal connectable to a device that is responsive to a second set of logic level signals. First and second power terminals are provided for connection to first and second power supplies, respectively. A transistor of first conductivity type having first, second and gate terminals is provided with the gate terminal connected to the input terminal and the first terminal connected to the first power supply terminal. A second transistor of opposite conductivity type having a first, second and gate terminal is provided with the gate terminal of the second transistor connected to the second terminal of the first transistor.

Abstract: A plurality of circuit embodiments, implemented in MOS, for receiving two non-overlapping clock signals provide a booting function to each clock signal and in response to respective control signals directs one or the other of the booted clock signals to a single output line. The control signal for the first clock can change during the alternate second clock time and is stable during the first clock time. Similarly, the control signal for the second clock can change during the alternate first clock time and is stable during the second clock time. For both control signals, a low level enables the respective boot circuit.

Abstract: The present invention is a temperature compensating circuit adapted for use with a CMOS to ECL interfacing circuit which uses one normally unused ECL logic gate, formed on a chip of many ECL logic gates for generating the supply voltages for the level interfacing circuit such that the output voltage levels from the interfacing circuit will automatically track with the temperature experienced by the chips' ECL logic gates.

Abstract: A circuit for improving the rise time of an electronic signal including a voltage generator for generating a reference voltage, a comparator for comparing the voltage of an electronic signal whose rise time is to be improved with the voltage of the reference voltage generator, and a current pulse generator controlled by the comparator for generating a current pulse of a predetermined duration responsive to the comparison of the comparator. The current pulse is of sufficient magnitude to assist the rise time of the electronic signal.