Patents by Inventor Ikuo Soga
Ikuo Soga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230324328Abstract: A gas sensor, which includes a solid electrolyte layer including positive charge carriers to which detection-target gas coordinates, an electrode arranged on part of a plane of the solid electrolyte layer, and a unit configured to accelerate movements of the positive charge carriers.Type: ApplicationFiled: June 7, 2023Publication date: October 12, 2023Applicant: FUJITSU LIMITEDInventors: Satoru MOMOSE, Osamu TSUBOI, Ikuo SOGA
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Patent number: 11719745Abstract: A semiconductor device includes: a substrate; a circuit element disposed on a first surface side of the substrate; a first transmission line disposed on the first surface side; a first terminal disposed on the first surface side; a first dielectric disposed in a part of the first transmission line; a second terminal disposed on a side of the first dielectric opposite to the first transmission line; a second transmission line disposed on the first surface side and has one end coupled to the circuit element; a third terminal disposed on the first surface side and coupled to the other end of the second transmission line; a second dielectric disposed in a part of the second transmission line; a fourth terminal disposed on a side of the second dielectric opposite to the second transmission line; and a conductor disposed on a second surface side of the substrate.Type: GrantFiled: August 31, 2022Date of Patent: August 8, 2023Assignee: FUJITSU LIMITEDInventors: Ikuo Soga, Yoichi Kawano
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Publication number: 20220413039Abstract: A semiconductor device includes: a substrate; a circuit element disposed on a first surface side of the substrate; a first transmission line disposed on the first surface side; a first terminal disposed on the first surface side; a first dielectric disposed in a part of the first transmission line; a second terminal disposed on a side of the first dielectric opposite to the first transmission line; a second transmission line disposed on the first surface side and has one end coupled to the circuit element; a third terminal disposed on the first surface side and coupled to the other end of the second transmission line; a second dielectric disposed in a part of the second transmission line; a fourth terminal disposed on a side of the second dielectric opposite to the second transmission line; and a conductor disposed on a second surface side of the substrate.Type: ApplicationFiled: August 31, 2022Publication date: December 29, 2022Applicant: FUJITSU LIMITEDInventors: Ikuo Soga, Yoichi Kawano
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Patent number: 11506707Abstract: A semiconductor device includes: a substrate; a circuit element disposed on a first surface side of the substrate; a first transmission line disposed on the first surface side; a first terminal disposed on the first surface side; a first dielectric disposed in a part of the first transmission line; a second terminal disposed on a side of the first dielectric opposite to the first transmission line; a second transmission line disposed on the first surface side and has one end coupled to the circuit element; a third terminal disposed on the first surface side and coupled to the other end of the second transmission line; a second dielectric disposed in a part of the second transmission line; a fourth terminal disposed on a side of the second dielectric opposite to the second transmission line; and a conductor disposed on a second surface side of the substrate.Type: GrantFiled: June 25, 2020Date of Patent: November 22, 2022Assignee: FUJITSU LIMITEDInventors: Ikuo Soga, Yoichi Kawano
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Patent number: 11424240Abstract: A semiconductor device includes an electric circuit configured to include, a transistor, a first pad coupled to a gate or a drain of the transistor, a second pad coupled to the gate or the drain of the transistor, a first wiring that extends from the gate or the drain of the transistor to the first pad, and a second wiring that diverges from the first wiring and extends to the second pad, and a redistribution layer formed over the electric circuit and configured to include a first redistribution coupled to the first pad, and a second redistribution coupled to the second pad to constitute a stub.Type: GrantFiled: October 2, 2019Date of Patent: August 23, 2022Assignee: FUJITSU LIMITEDInventors: Ikuo Soga, Yoichi Kawano
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Patent number: 11069634Abstract: An amplifier includes an amplifier circuit configured to include a transistor that amplifies a signal, an insulating film provided over the amplifier circuit, an input pad provided over the insulating film and coupled to the transistor through a wiring in the insulating film, an output pad provided over the insulating film and coupled to the transistor through the wiring in the insulating film, and a metal layer provided over the insulating film to be grounded, and configured to include an opening that extends in a second direction intersecting with a first direction in a plane direction, the signal propagating from the input pad to the output pad in the first direction, and the opening being at a position overlapping the transistor.Type: GrantFiled: October 24, 2019Date of Patent: July 20, 2021Assignee: FUJITSU LIMITEDInventors: Ikuo Soga, Yoichi Kawano
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Publication number: 20210011077Abstract: A semiconductor device includes: a substrate; a circuit element disposed on a first surface side of the substrate; a first transmission line disposed on the first surface side; a first terminal disposed on the first surface side; a first dielectric disposed in a part of the first transmission line; a second terminal disposed on a side of the first dielectric opposite to the first transmission line; a second transmission line disposed on the first surface side and has one end coupled to the circuit element; a third terminal disposed on the first surface side and coupled to the other end of the second transmission line; a second dielectric disposed in a part of the second transmission line; a fourth terminal disposed on a side of the second dielectric opposite to the second transmission line; and a conductor disposed on a second surface side of the substrate.Type: ApplicationFiled: June 25, 2020Publication date: January 14, 2021Applicant: FUJITSU LIMITEDInventors: Ikuo Soga, Yoichi Kawano
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Patent number: 10868573Abstract: An antenna integrated amplifier includes a board configured to include an antenna, a radiator that faces the board, a first supporter interposed between the board and the radiator to support the board with respect to the radiator, and configured to include an amplifier to amplify a signal communicated by the antenna, a first bump interposed between the board and the first supporter to be electrically coupled to the antenna and the amplifier, a second supporter interposed between the board and the radiator to support the board with respect to the radiator, and a second bump interposed between the board and the second supporter.Type: GrantFiled: September 25, 2019Date of Patent: December 15, 2020Assignee: FUJITSU LIMITEDInventors: Ikuo Soga, Yoichi Kawano
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Patent number: 10670552Abstract: A gas sensor, which includes a solid electrolyte layer including positive charge carriers to which detection-target gas coordinates, an electrode arranged on part of a plane of the solid electrolyte layer, and a unit configured to accelerate movements of the positive charge carriers.Type: GrantFiled: November 16, 2016Date of Patent: June 2, 2020Assignee: FUJITSU LIMITEDInventors: Satoru Momose, Osamu Tsuboi, Ikuo Soga
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Publication number: 20200161258Abstract: An amplifier includes an amplifier circuit configured to include a transistor that amplifies a signal, an insulating film provided over the amplifier circuit, an input pad provided over the insulating film and coupled to the transistor through a wiring in the insulating film, an output pad provided over the insulating film and coupled to the transistor through the wiring in the insulating film, and a metal layer provided over the insulating film to be grounded, and configured to include an opening that extends in a second direction intersecting with a first direction in a plane direction, the signal propagating from the input pad to the output pad in the first direction, and the opening being at a position overlapping the transistor.Type: ApplicationFiled: October 24, 2019Publication date: May 21, 2020Applicant: FUJITSU LIMITEDInventors: Ikuo Soga, Yoichi Kawano
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Publication number: 20200144249Abstract: A semiconductor device includes an electric circuit configured to include, a transistor, a first pad coupled to a gate or a drain of the transistor, a second pad coupled to the gate or the drain of the transistor, a first wiring that extends from the gate or the drain of the transistor to the first pad, and a second wiring that diverges from the first wiring and extends to the second pad, and a redistribution layer formed over the electric circuit and configured to include a first redistribution coupled to the first pad, and a second redistribution coupled to the second pad to constitute a stub.Type: ApplicationFiled: October 2, 2019Publication date: May 7, 2020Applicant: FUJITSU LIMITEDInventors: Ikuo Soga, Yoichi Kawano
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Patent number: 10637410Abstract: An amplification device includes a base metallic plate at a ground potential, an amplifier disposed on the base metallic plate, and including a plurality of transistors, and a matcher disposed on the base metallic plate so as to be coupled to the amplifier, the matcher performing impedance matching of output of the amplifier, wherein the matcher includes a first matching circuit board including a first dielectric board disposed on an upper surface of the base metallic plate, the first dielectric board having, on an upper surface, a transmission line coupled to an output electrode of the amplifier, and a second matching circuit board disposed so as to intersect the first matching circuit board, and disposed with a second dielectric board sandwiched by a first metallic film having one end coupled to the transmission line and having another end opened and a second metallic film at the ground potential.Type: GrantFiled: January 3, 2019Date of Patent: April 28, 2020Assignee: FUJITSU LIMITEDInventor: Ikuo Soga
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Patent number: 10637451Abstract: A pulse position modulation circuit includes a delay locked loop circuit configured to include a plurality of delay circuits coupled in a cascade, each of the plurality of delay circuits being configured to delay an input signal by a time width corresponding to a control signal so as to generate an output signal, a plurality of pulse generation circuits, each of which is configured to generate a pulse with a pulse width corresponding to a phase difference between a first signal and a second signal which have different phases from each other at different timings corresponding to states of the first signal and the second signal, each of the first signal and the second signal being the input signal or the output signal of the plurality of delay circuits, and a selection circuit configured to select pulses generated by the plurality of pulse generation circuits.Type: GrantFiled: July 25, 2019Date of Patent: April 28, 2020Assignee: FUJITSU LIMITEDInventor: Ikuo Soga
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Publication number: 20200127690Abstract: An antenna integrated amplifier includes a board configured to include an antenna, a radiator that faces the board, a first supporter interposed between the board and the radiator to support the board with respect to the radiator, and configured to include an amplifier to amplify a signal communicated by the antenna, a first bump interposed between the board and the first supporter to be electrically coupled to the antenna and the amplifier, a second supporter interposed between the board and the radiator to support the board with respect to the radiator, and a second bump interposed between the board and the second supporter.Type: ApplicationFiled: September 25, 2019Publication date: April 23, 2020Applicant: FUJITSU LIMITEDInventors: Ikuo Soga, Yoichi Kawano
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Publication number: 20200124563Abstract: A gas sensor, which includes a solid electrolyte layer including positive charge carriers to which detection-target gas coordinates, an electrode arranged on part of a plane of the solid electrolyte layer, and a unit configured to accelerate movements of the positive charge carriers.Type: ApplicationFiled: December 17, 2019Publication date: April 23, 2020Applicant: FUJITSU LIMITEDInventors: Satoru MOMOSE, Osamu TSUBOI, Ikuo SOGA
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Publication number: 20200075740Abstract: An amplifying device includes: a comb-shaped transistor that includes a comb-shaped source electrode having a plurality of source fingers; one or more resistors connected between the source electrode and a ground; and a plurality of capacitors connected between the source electrode and the ground, wherein the capacitors are separated from each other and arranged in a direction in which the source fingers are arranged.Type: ApplicationFiled: August 23, 2019Publication date: March 5, 2020Applicant: FUJITSU LIMITEDInventors: Masato Nishimori, Ikuo Soga, Tatsuya Hirose, Yoichi Kawano
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Publication number: 20200067496Abstract: A pulse position modulation circuit includes a delay locked loop circuit configured to include a plurality of delay circuits coupled in a cascade, each of the plurality of delay circuits being configured to delay an input signal by a time width corresponding to a control signal so as to generate an output signal, a plurality of pulse generation circuits, each of which is configured to generate a pulse with a pulse width corresponding to a phase difference between a first signal and a second signal which have different phases from each other at different timings corresponding to states of the first signal and the second signal, each of the first signal and the second signal being the input signal or the output signal of the plurality of delay circuits, and a selection circuit configured to select pulses generated by the plurality of pulse generation circuits.Type: ApplicationFiled: July 25, 2019Publication date: February 27, 2020Applicant: FUJITSU LIMITEDInventor: Ikuo Soga
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Publication number: 20190238102Abstract: An amplification device includes a base metallic plate at a ground potential, an amplifier disposed on the base metallic plate, and including a plurality of transistors, and a matcher disposed on the base metallic plate so as to be coupled to the amplifier, the matcher performing impedance matching of output of the amplifier, wherein the matcher includes a first matching circuit board including a first dielectric board disposed on an upper surface of the base metallic plate, the first dielectric board having, on an upper surface, a transmission line coupled to an output electrode of the amplifier, and a second matching circuit board disposed so as to intersect the first matching circuit board, and disposed with a second dielectric board sandwiched by a first metallic film having one end coupled to the transmission line and having another end opened and a second metallic film at the ground potential.Type: ApplicationFiled: January 3, 2019Publication date: August 1, 2019Applicant: FUJITSU LIMITEDInventor: Ikuo Soga
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Publication number: 20190214998Abstract: A delay locked loop circuit includes a first delay circuit that includes a plurality of first delay devices and a plurality of second delay devices, the plurality of first delay devices and the plurality of second delay devices are coupled in series with each other, a second delay circuit that includes a plurality of third delay devices equal in number and identical in configuration to the plurality of second delay devices, the plurality of third delay devices are coupled in series with each other, a phase comparator that outputs a phase difference between a first delayed clock output from the first delay circuit and a second delayed clock output from the second delay circuit, a first control circuit that outputs a first control signal that controls a time, and a second control circuit that outputs a second control signal.Type: ApplicationFiled: March 15, 2019Publication date: July 11, 2019Applicant: FUJITSU LIMITEDInventors: Ikuo Soga, Kazuaki Oishi, Hiroshi Matsumura, Yoichi Kawano, Yasuhiro Nakasha
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Patent number: 10348285Abstract: A detector circuit includes a first inverter including an input node coupled via a first capacitor to a transmission path for transmitting an AC signal, the first inverter outputting an output voltage in accordance with power of the AC signal, wherein the output voltage increases with increasing temperature, a second inverter including an input node coupled to the transmission path, the second inverter outputting an output voltage in accordance with power of the AC signal, wherein the output voltage decreases with increasing temperature, a third capacitor including one electrode coupled to either an output electrode of the first inverter or an output node of the second inverter, a first resistor coupled between the output node of the first inverter and an output node of the detector circuit, and a second resistor coupled between the output node of the second inverter and the output node of the detector circuit.Type: GrantFiled: August 21, 2018Date of Patent: July 9, 2019Assignee: FUJITSU LIMITEDInventor: Ikuo Soga