Abstract: A method of a first terminal may include: identifying first RB set(s) to be used for SL communication among consecutive RB sets through an LBT procedure; identifying a first subchannel group included in the first RB set(s) and a second subchannel group including a first PRB in the first RB set(s), the first PRB being not included in the first subchannel group; configuring the first PRB within the second subchannel group as an SL communication resource; and transmitting, to a second terminal, control information indicating that the first PRB is configured as the SL communication resource.

Abstract: A semiconductor device includes an active pattern including: a lower pattern extending in a first direction, and a plurality of sheet patterns spaced apart from the lower pattern in a second direction; a gate structure on the lower pattern and including a gate electrode and a gate insulating film including an interfacial insulating film including a first vertical portion and a horizontal portion. A dimension in a third direction of the first vertical portion is greater than a dimension in the second direction of the horizontal portion. The first vertical portion includes: a first area contacting a source/drain pattern; and a second area provided between the first area and the gate electrode. The interfacial insulating film includes a first element other than silicon, wherein a concentration of the first element in the first area is greater than a concentration of the first element in the second area.

Abstract: An airbag maintains deployment performance of an airbag cushion installed in a structure for dividing an occupant compartment space. The airbag includes an airbag cushion that includes a plurality of deployment areas and a spacing part that is disposed at a position adjacent to the plurality of deployment areas and separates the plurality of deployment area from one another.

Abstract: An electronic device including a memory device with improved reliability is provided. The semiconductor device comprises a data pin configured to transmit a data signal, a command/address pin configured to transmit a command and an address, a command/address receiver connected to the command/address pin, and a computing unit connected to the command/address receiver, wherein the command/address receiver receives a first command and a first address from the outside through the command/address pin and generates a first instruction on the basis of the first command and the first address, and the computing unit receives the first instruction and performs computation based on the first instruction.

Abstract: A heat sink plate includes a first layer made of copper (Cu) or a copper (Cu) alloy, a second layer formed on the first layer and made of molybdenum (Mo) or an alloy that includes copper (Cu) and one or more components selected from molybdenum (Mo), tungsten (W), carbon (C), chromium (Cr), titanium (Ti), and beryllium (Be), a third layer formed on the second layer and made of copper (Cu) or a copper (Cu) alloy, a fourth layer formed on the third layer and made of molybdenum (Mo) or an alloy that includes copper (Cu) and one or more components selected from molybdenum (Mo), tungsten (W), carbon (C), chromium (Cr), titanium (Ti), and beryllium (Be), and a fifth layer formed on the fourth layer and made of copper (Cu) or a copper (Cu) alloy.

Abstract: A semiconductor package includes a chip stack having a plurality of semiconductor chips vertically stacked on a package substrate. A stress-equalizing chip is disposed on the chip stack, the stress-equalizing chip providing means to reduce the variation in the electrical characteristics of the plurality of semiconductor chips. An encapsulant is disposed on the package substrate and is configured to cover at least a portion of the chip stack. Each of the plurality of semiconductor chips is electrically connected to the package substrate. The stress-equalizing chip is not electrically connected to the substrate or to the plurality of semiconductor chips.

Abstract: A heat sink plate includes a first layer made of copper (Cu) or a copper (Cu) alloy, a second layer formed on the first layer and made of molybdenum (Mo) or an alloy that includes copper (Cu) and one or more components selected from molybdenum (Mo), tungsten (W), carbon (C), chromium (Cr), titanium (Ti), and beryllium (Be), a third layer formed on the second layer and made of copper (Cu) or a copper (Cu) alloy, a fourth layer formed on the third layer and made of molybdenum (Mo) or an alloy that includes copper (Cu) and one or more components selected from molybdenum (Mo), tungsten (W), carbon (C), chromium (Cr), titanium (Ti), and beryllium (Be), and a fifth layer formed on the fourth layer and made of copper (Cu) or a copper (Cu) alloy.

Abstract: A heat sink plate having a structure in which two or more kinds of materials are laminated, includes: a core layer in the thickness direction of the heat sink plate; and cover layers covering a top surface and a bottom surface of the core layer; wherein the cover layers comprise a material containing copper, wherein the core layer is formed of a matrix having a first thermal expansion coefficient and a plurality of layers extending in parallel along the thickness direction of the core layer in a lattice form in the matrix, wherein the plurality of layers are made of an alloy having a second thermal expansion coefficient.

Abstract: A semiconductor package includes a chip stack having a plurality of semiconductor chips vertically stacked on a package substrate. A stress-equalizing chip is disposed on the chip stack, the stress-equalizing chip providing means to reduce the variation in the electrical characteristics of the plurality of semiconductor chips. An encapsulant is disposed on the package substrate and is configured to cover at least a portion of the chip stack. Each of the plurality of semiconductor chips is electrically connected to the package substrate. The stress-equalizing chip is not electrically connected to the substrate or to the plurality of semiconductor chips.

Abstract: A heat sink plate having a structure in which two or more kinds of materials are laminated, includes: a core layer in the thickness direction of the heat sink plate; and cover layers covering a top surface and a bottom surface of the core layer; wherein the cover layers comprise a material containing copper, wherein the core layer is formed of a matrix having a first thermal expansion coefficient and a plurality of layers extending in parallel along the thickness direction of the core layer in a lattice form in the matrix, wherein the plurality of layers are made of an alloy having a second thermal expansion coefficient.

Abstract: Provided are a transparent display device and a method for controlling same. This transparent display device comprises: a sensor which measures the color properties of light that is incident to the transparent display device; a light control unit which is configured so as to control the amount of light that is incident to the rear surface of the transparent display unit and penetrates a plurality of penetration units; and a transparent display panel which comprises a control unit configured so as to correct color distortion by making a comparison with a preset threshold value on the basis of the measured color properties and correcting the image to be displayed on a plurality of pixels, the transparent display panel displaying the corrected input image.

Abstract: A heat-dissipating plate comprises a core layer; and two cover layers formed by being laminated on the top and bottom face of the core layer, wherein, the core layer is composed of a composite material in which a carbon phase is composited in a Cu matrix, the cover layer is composed of a Mo—Cu alloy, and the thermal conductivity in the thickness direction of the heat-dissipating plate is at least 300 W/mK, and the thermal expansion coefficient of the heat-dissipating plate in a direction perpendicular to the thickness direction is at most 9×10-6/K.