Abstract: Semiconductor assemblies include a first package, each having at least one die affixed to, and electrically interconnected with, a die attach side of the first package substrate, and a second substrate having a first side and a second (“land”) side, mounted over the molding of the first package with the first side of the second substrate facing the die attach side of the first package substrate. Accordingly, the die attach sides of the first substrate and the first side of the second substrate face one another, and the “land” sides of the substrates face away from one another. Z-interconnection of the package and the substrate is by wire bonds connecting the first and second substrates. The assembly is encapsulated in such a way that both the land side of the second substrate (one side of the assembly) and a portion of the land side of the first package substrate (on the opposite side of the assembly) are exposed, so that second level interconnection and interconnection with additional components may be made.

Abstract: An encapsulant cavity integrated circuit package system including forming a first integrated circuit package with an inverted bottom terminal having an encapsulant cavity and an interposer, and attaching a component on the interposer in the encapsulant cavity.

Abstract: A semiconductor package includes a substrate. A crenellated spacer is attached to the substrate. At least one top die is attached to the crenellated spacer. The at least one top die is wire bonded to the substrate, and an encapsulant is formed over the crenellated spacer and the at least one top die.

Abstract: An integrated circuit die is provided having a body portion having a singulation side and a pedestal portion extending from the body portion and having a singulation side coplanar with the singulation side of the body portion.

Abstract: A method for manufacturing an integrated circuit package comprises forming a substrate by forming a core layer with a through opening and vias. A first conductive layer is formed on the core layer covering the through opening and a second conductive layer is formed on the core layer opposite the first conductive layer in the through opening and in the vias contacting the first conductive layer. An integrated circuit die is bonded to the second conductive layer and in the through opening. Connections are formed between the integrated circuit die and the second conductive layer, and the integrated circuit die and the connections are encapsulated.

Abstract: An electronic device having a substrate carrier is provided. A semiconductor connected to the substrate carrier. A heat spreader having upper and lower surfaces and legs recessed below the lower surface is connected to the substrate carrier. The Z-dimension between the heat spreader and the substrate carrier is maintained over substantially the entire area of the substrate carrier.

Abstract: A semiconductor package and method for fabricating the same is disclosed. In one embodiment, the semiconductor package includes a circuit board, at least two semiconductor chips, electric connection means, an encapsulant, and a plurality of conductive balls. The circuit board has a resin layer and a circuit pattern. The resin layer is provided with an opening at its center portion. The circuit pattern is formed on at least one of upper and lower surfaces of the resin layer and includes one or more bond fingers and ball lands exposed to the outside. The semiconductor chips have a plurality of input/output pads on an active surface thereof. The semiconductor chips are stacked at a position of the opening of the circuit board, with at least one of the chips being within the opening. Alternatively, both chips are in the opening. The electric connection means connects the input/output pads of the semiconductor chips to the bond fingers of the circuit board.

Abstract: A system is provided for an integrated circuit package including a leadframe having a lead finger. A groove is formed in a lead finger for a conductive bonding agent and a passive device is placed in the groove to be held by the conductive bonding agent.

Abstract: A method for fabricating a semiconductor package with a substrate in a strip format is provided. Semiconductor devices are attached in a strip format to the substrate, and a thermal interface material is applied to the semiconductor devices. A flat panel heat spreader is attached to each semiconductor device. The semiconductor devices are encapsulated with open encapsulation, leaving the surface of the flat panel heat spreader opposite the substrate externally exposed. Individual semiconductor packages are then singulated from the strip format.

Abstract: A fabrication method of a self-aligned ferroelectric gate transistor using a buffer layer of high etching selectivity is disclosed. A stacked structure is formed with a buffer layer with high etching selectivity inserted between a silicon substrate and a ferroelectric layer, and etching is performed on a portion where a source and a drain will be formed and then stopped at the buffer layer, thereby fabricating a self-aligned ferroelectric gate transistor without damage to the silicon thin film, and thus, an integration degree of a chip can be improved.

Abstract: A method for fabricating a semiconductor heat spreader from a unitary metallic plate is provided. The unitary metallic plate is formed into a panel, channel walls, at least two feet, and at least one external reversing bend. The channel walls depend from the panel to define a channel between the channel walls and the panel for receiving a semiconductor therein. The feet extend from respective channel walls for attachment to a substrate.

Abstract: A stacked semiconductor package includes a substrate and a first semiconductor device on the substrate. An interposer is supported above the first semiconductor device opposite the substrate. The interposer is electrically connected to the substrate. A second semiconductor device is mounted on the interposer.

Abstract: An integrated circuit package is provided. A substrate is provided having solder openings therein and a conductive layer thereon. The conductive layer is processed to form a plurality of pads over the solder openings in the substrate. A mask is formed over the plurality of pads and openings formed in the mask over at least two pads of the plurality of pads. An integrated circuit die is bonded over the substrate using a conductive adhesive where the conductive adhesive is placed in the openings in conductive contact with at least two pads of the plurality of pads.

Abstract: A method for fabricating a heat spreader is provided. Heat spreaders are formed and surrounded by a frame. The heat spreaders and frame are connected to one another by tie bars, the heat spreaders and tie bars having respective upper surfaces. At least portions of the upper surfaces of the tie bars are thinned to reduce the heights of the tie bars at least on a singulation line thereon. The frame is formed to support the heat spreader upper surfaces in an elevated position with respect thereto.

Abstract: A method for forming a heat spreader, and the heat spreader formed thereby, are disclosed. An array heat spreader having a plurality of connected heat spreader panels is formed. Slots are formed in opposing sides of the heat spreader panels. Legs are formed on and extending downwardly from each of the heat spreader panels in at least an opposing pair of the slots on the heat spreader panels. The legs are integral with the respective heat spreader panels from which they depend.

Abstract: An embodiment of the present invention allows mold compound to flow underneath a substrate where the mold compound will remain in place until the process of mold formation is completed. The mold compound of the package will penetrate all available cavities where the mold compound will remain in place and harden. After hardening, the mold compound surrounding a mold anchor will support an anchored area.

Abstract: The driving circuit for an NDRO-FRAM includes several NDRO-FRAM (Non Destructive Non Volatile Ferroelectric Random Access Memory) cells each having a drain, a bulk, a source and a gate and arranged as a matrix. A plurality of reading word lines are separately connected to each drain of the NDRO-FRAM cells arranged in columns, and a plurality of writing word lines are separately connected to each bulk of the NDRO-FRM cells arranged in columns. Several data level transmission circuits for transmitting a data level of the NDRO-FRAM cells are also included, which are connected to a plurality of data level transmission circuits. Accordingly, the present invention is capable of reading and writing of data on the NDRO-FRAM cells.

Abstract: The driving circuit for an NDRO-FRAM includes several NDRO-FRAM (Non Destructive Non Volatile Ferroelectric Random Access Memory) cells each having a drain, a bulk, a source and a gate and arranged as a matrix. A plurality of reading word lines are separately connected to each drain of the NDRO-FRAM cells arranged in columns, and a plurality of writing word lines are separately connected to each bulk of the NDRO-FRM cells arranged in columns. Several data level transmission circuits for transmitting a data level of the NDRO-FRAM cells are also included, which are connected to a plurality of data level transmission circuits. Accordingly, the present invention is capable of reading and writing of data on the NDRO-FRAM cells.