Patents by Inventor Il-Woo Kim
Il-Woo Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240155505Abstract: A method of a first user equipment (UE) may comprise: receiving a downlink (DL) reference signal transmitted by a base station using a beam included in a beam candidate group to be used for sidelink (SL) communication with a second UE; measuring a DL reference signal received power (RSRP) of the DL reference signal; determining a transmit power of a beam included in the beam candidate group based on the measured DL RSRP; and transmitting SL data to the second UE with the determined transmit power.Type: ApplicationFiled: October 31, 2023Publication date: May 9, 2024Inventors: Jun Hyeong KIM, Go San NOH, Seon Ae KIM, Il Gyu KIM, Hee Sang CHUNG, Dae Soon CHO, Sung Woo CHOI, Seung Nam CHOI, Jung Pil CHOI
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Patent number: 11977703Abstract: A touch detection module, includes: a plurality of driving electrodes arranged side by side; a plurality of sensing electrodes staggered with respect to the driving electrodes; and a touch driving circuit configured to supply touch driving signals to the plurality of driving electrodes and to detect touch detection signals through the plurality of sensing electrodes to identify touch position coordinates, wherein the touch driving circuit is configured: to vary frequency modulation parameter set values in response to a change in a frequency of reference clocks, and to generate and supply a frequency of the touch driving signals by using the reference clocks and a varied frequency modulation parameter set value.Type: GrantFiled: February 24, 2023Date of Patent: May 7, 2024Assignee: Samsung Display Co., Ltd.Inventors: Jin Woo Park, Min Hong Kim, Tae Joon Kim, Il Ho Lee, Wan Kee Jun
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Publication number: 20240120974Abstract: A wireless communication method and apparatus in a wireless local area network (WLAN) system are disclosed. A wireless communication method according to one embodiment may include generating a high-efficiency Wi-Fi (HEW) frame including at least one of an HEW-SIG-A field and an HEW-SIG-B field which include channel information for communications according to an Orthogonal Frequency-Division Multiple Access (OFDMA) mode, and transmitting the generated HEW frame to a reception apparatus.Type: ApplicationFiled: December 21, 2023Publication date: April 11, 2024Inventors: Yu Ro LEE, Jae Woo PARK, Jae Seung LEE, Jee Yon CHOI, Il Gyu KIM, Seung Chan BANG
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Publication number: 20240114414Abstract: Provided are a method and apparatus for providing a network switching service to a user equipment.Type: ApplicationFiled: October 4, 2023Publication date: April 4, 2024Applicant: KT CORPORATIONInventors: Ji-Young JUNG, Kun-Woo PARK, Se-Hoon KIM, Il-Yong KIM, Sang-Hyun PARK, Ho-Jun JANG, Won-Chang CHO
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Patent number: 11947104Abstract: A spiral phase plate, according to one embodiment, for generating a Laguerre Gaussian beam by reflecting an incident beam emitted from a light source, may comprise: a first quadrant area in which the step height increase rate per unit angle decreases progressively in one direction from the point with the lowest step height to the point with the highest step height; and a second quadrant area in which the step height increase rate per unit angle increases progressively in the one direction.Type: GrantFiled: September 9, 2020Date of Patent: April 2, 2024Assignees: KOREA BASIC SCIENCE INSTITUTE, INSTITUTE FOR BASIC SCIENCE, GWANGJU INSTITUTE OF SCIENCE AND TECHNOLOGYInventors: I Jong Kim, Ji Yong Bae, Hong Seung Kim, Geon Hee Kim, Ki Soo Chang, Cheonha Jeon, Il Woo Choi, Chang Hee Nam
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Publication number: 20240106794Abstract: Provided are a method and apparatus for a user equipment, a core network, and a second device to enable bidirectional communication for second devices. The method of the second device may include receiving internet protocol (IP) configuration information for automatically configuring an IP version 6 (IPv6) address of the second device from a core network through a user equipment; generating the IPv6 address using information in the IP configuration information; and transmitting the generated IPv6 address to the core network through the UE.Type: ApplicationFiled: September 6, 2023Publication date: March 28, 2024Applicant: KT CORPORATIONInventors: Won-Chang CHO, Se-Hoon KIM, Il-Yong KIM, Kun-Woo PARK, Sang-Hyun PARK, Ho-Jun JANG, Ji-Young JUNG
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Patent number: 11935703Abstract: A multilayer electronic component has a body and a non-conductive resin layer. The non-conductive resin layer includes a body cover portion disposed in a region of an external surface of the body in which an electrode layer of an external electrode is not disposed, and an extending portion extending from the body cover portion between the electrode layer and a conductive resin layer of the external electrode, to thereby suppress arc discharge, improve bending strength, and improve moisture resistance.Type: GrantFiled: January 9, 2023Date of Patent: March 19, 2024Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Jae Seok Yi, Jung Min Kim, Bon Seok Koo, Chang Hak Choi, Il Ro Lee, Byung Woo Kang, San Kyeong, Hae Sol Kang
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Patent number: 11700731Abstract: A method of manufacturing a vertical memory device includes forming a first sacrificial layer on a substrate, the first sacrificial layer including a first insulating material, forming a mold including an insulation layer and a second sacrificial layer alternately and repeatedly stacked on the first sacrificial layer, the insulation layer and the second sacrificial layer including second and third insulating materials, respectively, different from the first insulating material, forming a channel through the mold and the first sacrificial layer, forming an opening through the mold and the first sacrificial layer to expose an upper surface of the substrate, removing the first sacrificial layer through the opening to form a first gap, forming a channel connecting pattern to fill the first gap, and replacing the second sacrificial layer with a gate electrode.Type: GrantFiled: June 15, 2021Date of Patent: July 11, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Il-Woo Kim, Sang-Ho Rha, Byoung-Deog Choi, Ik-Soo Kim, Min-Jae Oh
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Patent number: 11348938Abstract: In a method of manufacturing a vertical memory device, a first sacrificial layer including a nitride is formed on a substrate. A mold including an insulation layer and a second sacrificial layer alternately and repeatedly stacked on the first sacrificial layer is formed. The insulation layer and the second sacrificial layer include a first oxide and a second oxide, respectively. A channel is formed through the mold and the first sacrificial layer. An opening is formed through the mold and the first sacrificial layer to expose an upper surface of the substrate. The first sacrificial layer is removed through the opening to form a first gap. A channel connecting pattern is formed to fill the first gap. The second sacrificial layer is replaced with a gate electrode.Type: GrantFiled: June 19, 2019Date of Patent: May 31, 2022Inventors: Il-Woo Kim, Sang-Gi An, Hyun-Gon Pyo, Ik-Soo Kim, Hee-Sook Park, Ji-Woon Im
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Patent number: 11233494Abstract: An electronic circuit includes a first filter and a second filter. The first filter passes a first frequency component of a first harmonic frequency generated by a first voltage source to form a potential difference in a chamber and a second frequency component of a second harmonic frequency higher than the first harmonic frequency. The second filter removes the first frequency component and the second frequency component received from the first filter. The second harmonic frequency is included in a first frequency band determined based on a capacitance of the second filter.Type: GrantFiled: October 4, 2019Date of Patent: January 25, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Hyungjoon Kim, Je-Dong Lee, Younghoon Kwon, Myoungwoon Kim, Il-Woo Kim, Jiwoon Im, Jaewon Jung, Hee Jong Jeong
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Publication number: 20210313347Abstract: A method of manufacturing a vertical memory device includes forming a first sacrificial layer on a substrate, the first sacrificial layer including a first insulating material, forming a mold including an insulation layer and a second sacrificial layer alternately and repeatedly stacked on the first sacrificial layer, the insulation layer and the second sacrificial layer including second and third insulating materials, respectively, different from the first insulating material, forming a channel through the mold and the first sacrificial layer, forming an opening through the mold and the first sacrificial layer to expose an upper surface of the substrate, removing the first sacrificial layer through the opening to form a first gap, forming a channel connecting pattern to fill the first gap, and replacing the second sacrificial layer with a gate electrode.Type: ApplicationFiled: June 15, 2021Publication date: October 7, 2021Inventors: Il-Woo KIM, Sang-Ho RHA, Byoung-Deog CHOI, Ik-Soo KIM, Min-Jae OH
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Patent number: 11063060Abstract: A method of manufacturing a vertical memory device includes forming a first sacrificial layer on a substrate, the first sacrificial layer including a first insulating material, forming a mold including an insulation layer and a second sacrificial layer alternately and repeatedly stacked on the first sacrificial layer, the insulation layer and the second sacrificial layer including second and third insulating materials, respectively, different from the first insulating material, forming a channel through the mold and the first sacrificial layer, forming an opening through the mold and the first sacrificial layer to expose an upper surface of the substrate, removing the first sacrificial layer through the opening to form a first gap, forming a channel connecting pattern to fill the first gap, and replacing the second sacrificial layer with a gate electrode.Type: GrantFiled: June 27, 2019Date of Patent: July 13, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Il-Woo Kim, Sang-Ho Rha, Byoung-Deog Choi, Ik-Soo Kim, Min-Jae Oh
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Publication number: 20200199752Abstract: A baffle including a base plate disposed in a central portion of a showerhead in an apparatus for processing a substrate. An extension plate is movably connected to a planar surface of the base plate. The extension plate is configured to extend and contract radially from the base plate to change a diameter of the baffle.Type: ApplicationFiled: July 15, 2019Publication date: June 25, 2020Inventors: MIN-JOON KIM, MYOUNG-WOON KIM, HEE-JONG JEONG, IL-WOO KIM, JAE-HOON PARK, JI-WOON IM, HYUN-GON PYO
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Publication number: 20200204143Abstract: An electronic circuit includes a first filter and a second filter. The first filter passes a first frequency component of a first harmonic frequency generated by a first voltage source to form a potential difference in a chamber and a second frequency component of a second harmonic frequency higher than the first harmonic frequency. The second filter removes the first frequency component and the second frequency component received from the first filter. The second harmonic frequency is included in a first frequency band determined based on a capacitance of the second filter.Type: ApplicationFiled: October 4, 2019Publication date: June 25, 2020Inventors: Hyungjoon KIM, Je-Dong LEE, Younghoon KWON, Myoungwoon KIM, Il-Woo KIM, Jiwoon IM, Jaewon JUNG, Hee Jong JEONG
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Publication number: 20200168628Abstract: In a method of manufacturing a vertical memory device, a first sacrificial layer including a nitride is formed on a substrate. A mold including an insulation layer and a second sacrificial layer alternately and repeatedly stacked on the first sacrificial layer is formed. The insulation layer and the second sacrificial layer include a first oxide and a second oxide, respectively. A channel is formed through the mold and the first sacrificial layer. An opening is formed through the mold and the first sacrificial layer to expose an upper surface of the substrate. The first sacrificial layer is removed through the opening to form a first gap. A channel connecting pattern is formed to fill the first gap. The second sacrificial layer is replaced with a gate electrode.Type: ApplicationFiled: June 19, 2019Publication date: May 28, 2020Inventors: IL-WOO KIM, SANG-GI AN, HYUN-GON PYO, IK-SOO KIM, HEE-SOOK PARK, JI-WOON IM
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Publication number: 20200135760Abstract: A method of manufacturing a vertical memory device includes forming a first sacrificial layer on a substrate, the first sacrificial layer including a first insulating material, forming a mold including an insulation layer and a second sacrificial layer alternately and repeatedly stacked on the first sacrificial layer, the insulation layer and the second sacrificial layer including second and third insulating materials, respectively, different from the first insulating material, forming a channel through the mold and the first sacrificial layer, forming an opening through the mold and the first sacrificial layer to expose an upper surface of the substrate, removing the first sacrificial layer through the opening to form a first gap, forming a channel connecting pattern to fill the first gap, and replacing the second sacrificial layer with a gate electrode.Type: ApplicationFiled: June 27, 2019Publication date: April 30, 2020Inventors: Il-Woo KIM, Sang-Ho RHA, Byoung-Deog CHOI, Ik-Soo KIM, Min-Jae OH
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Patent number: 10325922Abstract: A semiconductor device includes a substrate, a stacked structure of insulating layers and gate electrodes alternately and repeatedly stacked on the substrate, and a pillar passing through the stacked-layer structure. The insulating layers include lower insulating layers, intermediate insulating layers disposed on the lower insulating layers, and upper insulating layers disposed on the intermediate insulating layers. The lower insulating layers have a hardness less than that of the intermediate insulating layers, and the upper insulating layers have a hardness greater than that of the intermediate insulating layers.Type: GrantFiled: November 17, 2017Date of Patent: June 18, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Yeong Dae Lim, Seung Jae Jung, Jin Young Bang, Il Woo Kim, Ho Gil Jung
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Publication number: 20180350830Abstract: A semiconductor device includes a substrate, a stacked structure of insulating layers and gate electrodes alternately and repeatedly stacked on the substrate, and a pillar passing through the stacked-layer structure. The insulating layers include lower insulating layers, intermediate insulating layers disposed on the lower insulating layers, and upper insulating layers disposed on the intermediate insulating layers. The lower insulating layers have a hardness less than that of the intermediate insulating layers, and the upper insulating layers have a hardness greater than that of the intermediate insulating layers.Type: ApplicationFiled: November 17, 2017Publication date: December 6, 2018Inventors: YEONG DAE LIM, SEUNG JAE JUNG, JIN YOUNG BANG, IL WOO KIM, HO GIL JUNG
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Patent number: 10008410Abstract: A deposition apparatus includes a chamber, a plate in the chamber and configured support a substrate, a deposition unit configured to perform a deposition process in-situ in the chamber, and a UV annealing unit configured to perform a first ultraviolet (UV) and a second ultraviolet (UV) annealing process in-situ in the chamber. The deposition process may include sequentially depositing a first sacrificial layer, a first oxide layer, a second sacrificial layer and a second oxide layer on the substrate. The first UV annealing process may be performed on the first oxide layer after the first oxide layer is deposited. The second UV annealing process may be different from the first UV annealing process and may be performed on the second oxide layer after the second oxide layer is deposited.Type: GrantFiled: March 21, 2017Date of Patent: June 26, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Kwang Chul Park, Ji Woon Im, Dai Hong Kim, Il Woo Kim, Hyun Seok Lim
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Patent number: 9299826Abstract: A memory device includes a gate structure, a contact plug, and a spacer. The gate structure includes first and second conductive layer patterns sequentially stacked on a substrate. The contact plug passes through the second conductive layer pattern, and a sidewall of the contact plug directly contacts at least a portion of the second conductive layer pattern. The spacer surrounds a portion of the sidewall of the contact plug and contacting the gate structure.Type: GrantFiled: March 11, 2014Date of Patent: March 29, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hauk Han, Il-Woo Kim, Jeong-Gil Lee, Yong-Il Kwon, Myoung-Bum Lee