Abstract: A deposition apparatus includes a chamber, a plate in the chamber and configured support a substrate, a deposition unit configured to perform a deposition process in-situ in the chamber, and a UV annealing unit configured to perform a first ultraviolet (UV) and a second ultraviolet (UV) annealing process in-situ in the chamber. The deposition process may include sequentially depositing a first sacrificial layer, a first oxide layer, a second sacrificial layer and a second oxide layer on the substrate. The first UV annealing process may be performed on the first oxide layer after the first oxide layer is deposited. The second UV annealing process may be different from the first UV annealing process and may be performed on the second oxide layer after the second oxide layer is deposited.

Abstract: A memory device includes a gate structure, a contact plug, and a spacer. The gate structure includes first and second conductive layer patterns sequentially stacked on a substrate. The contact plug passes through the second conductive layer pattern, and a sidewall of the contact plug directly contacts at least a portion of the second conductive layer pattern. The spacer surrounds a portion of the sidewall of the contact plug and contacting the gate structure.

Abstract: In the method, a plurality of gate structures may be formed on a substrate and be spaced apart from each other in a first direction. An insulation layer pattern may be formed by performing a chemical vapor deposition process using SiH4 gas as a source gas. The insulation layer pattern may partially define an air gap between the adjacent gate structures. A width of the air gap in the first direction may be about 65% to about 70% of a distance between the adjacent gate structures.

Abstract: A memory device includes a gate structure, a contact plug, and a spacer. The gate structure includes first and second conductive layer patterns sequentially stacked on a substrate. The contact plug passes through the second conductive layer pattern, and a sidewall of the contact plug directly contacts at least a portion of the second conductive layer pattern. The spacer surrounds a portion of the sidewall of the contact plug and contacting the gate structure.

Abstract: A MEMS (Micro Electro Mechanical System) device and a method of manufacturing the same, in which an detection indicator is formed on a chamber layer stacked on a substrate such that a user easily inspects whether the chamber layer has a required thickness. The MEMS device can include two detection indicators that are formed on the chamber layer and have different depth from each other, or an detection indicator which is formed on the chamber layer and has a tapered sectional shape in which an upper surface of the detection indicator is gradually narrowed in a downward direction such that a user can easily inspect whether the chamber layer has a required thickness. The user can precisely determine whether the chamber layer is planarized to a required thickness by planarizing the detection indicator formed on the chamber layer, and inspecting the detection indicator by using an optical microscope, thereby facilitating inspection for a thickness of the chamber layer.

Abstract: An isolation layer structure includes first to fourth oxide layer patterns. The first and third oxide layer patterns are sequentially formed in a first trench defined by a first recessed top surface of a substrate and sidewalls of gate structures on the substrate in a first region. The first trench has a first width, and the first and third oxide layer patterns have no void therein. The second and fourth oxide layer patterns are sequentially formed in a second trench defined by a second recessed top surface of the substrate and sidewalls of gate structures on the substrate in a second region. The second trench has a second width larger than the first width, and the fourth oxide layer pattern has a void therein.

Abstract: An isolation layer structure includes first to fourth oxide layer patterns. The first and third oxide layer patterns are sequentially formed in a first trench defined by a first recessed top surface of a substrate and sidewalls of gate structures on the substrate in a first region. The first trench has a first width, and the first and third oxide layer patterns have no void therein. The second and fourth oxide layer patterns are sequentially formed in a second trench defined by a second recessed top surface of the substrate and sidewalls of gate structures on the substrate in a second region. The second trench has a second width larger than the first width, and the fourth oxide layer pattern has a void therein.

Abstract: An isolation layer structure includes first to fourth oxide layer patterns. The first and third oxide layer patterns are sequentially formed in a first trench defined by a first recessed top surface of a substrate and sidewalls of gate structures on the substrate in a first region. The first trench has a first width, and the first and third oxide layer patterns have no void therein. The second and fourth oxide layer patterns are sequentially formed in a second trench defined by a second recessed top surface of the substrate and sidewalls of gate structures on the substrate in a second region. The second trench has a second width larger than the first width, and the fourth oxide layer pattern has a void therein.

Abstract: An isolation layer structure includes first to fourth oxide layer patterns. The first and third oxide layer patterns are sequentially formed in a first trench defined by a first recessed top surface of a substrate and sidewalls of gate structures on the substrate in a first region. The first trench has a first width, and the first and third oxide layer patterns have no void therein. The second and fourth oxide layer patterns are sequentially formed in a second trench defined by a second recessed top surface of the substrate and sidewalls of gate structures on the substrate in a second region. The second trench has a second width larger than the first width, and the fourth oxide layer pattern has a void therein.

Abstract: Disclosed is a method of manufacturing an inkjet printhead. The method includes: forming a chamber layer comprising a plurality of ink chambers on a substrate; forming a sacrificial layer comprising water soluble polymer on the chamber layer so as to fill the ink chambers; forming a nozzle layer comprising a plurality of nozzles on the sacrificial layer and the chamber layer; forming an ink feed hole for ink supply in the substrate; and removing the sacrificial layer. The sacrificial layer and the chamber layer may be planarized using a chemical mechanical polishing (CMP) process. The CMP process may utilize a hard polishing, in which an oil based slurry along with polishing pad of hard material to reduce the occurrences of dishing phenomenon.

Abstract: A MEMS (Micro Electro Mechanical System) device and a method of manufacturing the same, in which an detection indicator is formed on a chamber layer stacked on a substrate such that a user easily inspects whether the chamber layer has a required thickness. The MEMS device can include two detection indicators that are formed on the chamber layer and have different depth from each other, or an detection indicator which is formed on the chamber layer and has a tapered sectional shape in which an upper surface of the detection indicator is gradually narrowed in a downward direction such that a user can easily inspect whether the chamber layer has a required thickness. The user can precisely determine whether the chamber layer is planarized to a required thickness by planarizing the detection indicator formed on the chamber layer, and inspecting the detection indicator by using an optical microscope, thereby facilitating inspection for a thickness of the chamber layer.

Abstract: A method of manufacturing a thermal inkjet printhead. The method includes forming on a substrate a chamber layer having an ink chamber, forming a sacrificial layer on the chamber layer wherein the sacrificial layer fills the ink chamber, and planarizing a top surface of the sacrificial layer and of the chamber layer using a primary Chemical Mechanical Polishing (CMP) process until the sacrificial layer and the chamber layer attain a desired height, wherein a slurry is used in the primary CMP process that includes polishing particles having an average particle size of 500 nm˜2 ?m.