Abstract: Disclosed are a method and an apparatus of near field scan calibration, and more particularly, a method and an apparatus for near field scan calibration for calibrating a characteristic of an antenna for near field scan measurement of a semiconductor chip. The apparatus for near field scan calibration includes: a plane-type text fixture having a plane shape; an antenna positioned spaced apart from the plane-type test fixture by a set spacing distance and acquiring data including a magnetic field; and a spectrum analyzer analyzing the data acquired by the antenna.

Abstract: Provided is an electromagnetic interference (EMI) measuring device. The EMI measuring device according to the present invention includes an electromagnetic wave eliminating unit eliminating remaining electromagnetic waves from a DUT in response to an eliminating control signal of the control unit. The control unit may calculate EMI of the DUT on the basis of a measured result measured before the elimination of remaining electromagnetic waves. The EMI measuring device according to the present invention may compensate for an error due to remaining electromagnetic waves and measure EMI at high accuracy.

Abstract: A semiconductor package is provided. The semiconductor package includes a package body, a plurality of semiconductor chips, and an external connection terminal. The package body is stacked with a plurality of sheets where conductive patterns and vias are disposed. The plurality of semiconductor chips are inserted into insert slots extending from one surface of the package body. The external connection terminal is provided on other surface opposite to the one surface of the package body. Here, the plurality of semiconductor chips are electrically connected to the external connection terminal.

Abstract: Disclosed are a method and an apparatus of designing a semiconductor chip. The disclosed method includes the steps of: storing a plurality of EMS (Electro Magnetic Susceptibility) semiconductor IPs (Intellectual Property) and a plurality of EMI (Electro Magnetic Interference) semiconductor IPs; selecting a proper semiconductor IP from among the plurality of EMS shielding semiconductor IPs in a case of an input pin, and selecting a proper semiconductor IP from among the plurality of EMI shielding semiconductor IPs in a case of an output pin; and designing the semiconductor chip by disposing the selected semiconductor IP.

Abstract: Provided is an Electromagnetic Interference (EMI) reduction apparatus. The EMI reduction apparatus includes: an electromagnetic wave absorbing unit absorbing electromagnetic waves from an electromagnetic wave generator and converting the absorbed electromagnetic waves into thermal energy through thermal conversion and emitting the thermal energy; and a thermoelectric unit converting the emitted thermal energy into electric energy.

Abstract: An optical device includes a first waveguide extended in one direction. A second waveguide is positioned at a side of the first waveguide. The second waveguide includes the first conductive semiconductor layer, the second conductive semiconductor layer, and the undoped semiconductor layer positioned between the first conductive semiconductor layer and the second conductive semiconductor layer, wherein the undoped semiconductor layer has a refractive index larger than those of the first conductive semiconductor layer and the second conductive semiconductor layer. First and second electrodes are connected to the first conductive semiconductor layer and the second conductive semiconductor layer of the second waveguide, respectively.

Abstract: Systems, methods and computer program products for facilitating access to an application or action directly from a lock screen user interface while interacting with a (mobile) computing device are disclosed. Such systems, methods and computer program products provide a multi-stage approach—a first user input-based component (e.g., touch, swipe, voice commands) within a security user interface (e.g., lock screen user interface) followed by a second application or action-based component (e.g., action shortcut and/or action) launched directly from the security user interface. That is, to deactivate the lock screen user interface, the user provides an authorized user input at the computing device. Second, to access the application or action, an application or action shortcut user interface is automatically displayed or the application or action is automatically launched; both directly from the lock screen user interface without requiring any additional user interaction.

Abstract: A method of fabricating nanostructure for antireflection and a method of fabricating a photo device integrated with the nanostructure for antireflection are provided. The fabrication of the nanostructure for antireflection includes coating a solution containing a combination of metal ions with organic or inorganic ions on a substrate, sintering the coated solution using an annealing process to grow nanoscale metal particles, and chemically etching the substrate using the metal particles as mask or accelerator to form a subwavelength nanostructure on the surface of the substrate, thereby manufacturing the nanostructure for antireflection without an apparatus requiring a vacuum state using a simple method for a short amount of time to minimize reflection of light at an interface between a semiconductor material and the air, and producing a photo device having good luminous efficiency and performance at low cost in large quantities by applying it to the photo device.

Abstract: A semiconductor package is provided. The semiconductor package includes a package body, a plurality of semiconductor chips, and an external connection terminal. The package body is stacked with a plurality of sheets where conductive patterns and vias are disposed. The plurality of semiconductor chips are inserted into insert slots extending from one surface of the package body. The external connection terminal is provided on other surface opposite to the one surface of the package body. Here, the plurality of semiconductor chips are electrically connected to the external connection terminal.

Abstract: Disclosed are a method and an apparatus of near field scan calibration, and more particularly, a method and an apparatus for near field scan calibration for calibrating a characteristic of an antenna for near field scan measurement of a semiconductor chip. The apparatus for near field scan calibration includes: a plane-type text fixture having a plane shape; an antenna positioned spaced apart from the plane-type test fixture by a set spacing distance and acquiring data including a magnetic field; and a spectrum analyzer analyzing the data acquired by the antenna.

Abstract: Provided is a low power consumption processor. The processor includes: a plurality of blocks; a memory storing instructions that control each of the plurality of blocks; and a multi power controller generates a signal that activates at least one of the plurality of blocks according to an address storing the instruction, and provides a normal power voltage or a reduction power voltage in response to the activation signal.

Abstract: Provided is an Electromagnetic Interference (EMI) reduction apparatus. The EMI reduction apparatus includes: an electromagnetic wave absorbing unit absorbing electromagnetic waves from an electromagnetic wave generator and converting the absorbed electromagnetic waves into thermal energy through thermal conversion and emitting the thermal energy; and a thermoelectric unit converting the emitted thermal energy into electric energy.

Abstract: The present invention provides an apparatus and method for predicting a moving direction of another vehicle running on a carriageway adjacent to a user's vehicle using periodically acquired image information around the user's vehicle, and performing a control process of preventing collision of the user's vehicle when a moving direction of the user's vehicle crosses the moving direction of the other vehicle.

Abstract: Provided are an arithmetic method and device of a reconfigurable processor. The arithmetic device includes: an Arithmetic Logic Unit (ALU) for performing an addition and subtraction operation and a logic operation of a binary signal; a multiplier for performing a multiplication operation of the binary signal; a shifter for changing an arrangement of the binary signal; a first operand selector and a second operand selector each for selecting one of values output from the ALU, the multiplier, and the shifter; and an adder for adding the values selected by the first operand selector and the second operand selector.

Abstract: Provided is a parallel processor for supporting a floating-point operation. The parallel processor has a flexible structure for easy development of a parallel algorithm involving multimedia computing, requires low hardware cost, and consumes low power. To support floating-point operations, the parallel processor uses floating-point accumulators and a flag for floating-point multiplication. Using the parallel processor, it is possible to process a geometric transformation operation in a 3-dimensional (3D) graphics process at low cost. Also, the cost of a bus width for instructions can be minimized by a partitioned Single-Instruction Multiple-Data (SIMD) method and a method of conditionally executing instructions.

Abstract: Provided is a highly energy-efficient processor architecture. The architecture employs 2-stage dynamic voltage scaling (DVS) and a sleep mode for high energy efficiency, dynamically controls the power supply voltage and activation of an embedded processor with instructions, and thus can prevent performance deterioration while reducing power consumption.

Abstract: Provided are an apparatus and a method of managing a reconfiguration data memory. A space for a memory that stores configuration data used for reconfiguration of a target system is not provided in the target system. Instead the configuration data is stored in a separate server and, if required, the configuration data is transmitted to the target system through an Internet. Data that should be preserved after the reconfiguration among data contents stored in SoC internal and external memories of the target system is transferred to the server. The emptied space of the SoC internal and external memories is used as a configuration memory. After the reconfiguration, the preservation data is returned to its original position in the memories.

Abstract: Provided is a parallel processor for supporting a floating-point operation. The parallel processor has a flexible structure for easy development of a parallel algorithm involving multimedia computing, requires low hardware cost, and consumes low power. To support floating-point operations, the parallel processor uses floating-point accumulators and a flag for floating-point multiplication. Using the parallel processor, it is possible to process a geometric transformation operation in a 3-dimensional (3D) graphics process at low cost. Also, the cost of a bus width for instructions can be minimized by a partitioned Single-Instruction Multiple-Data (SIMD) method and a method of conditionally executing instructions.

Abstract: Provided is a low power consumption processor. The processor includes: a plurality of blocks; a memory storing instructions that control each of the plurality of blocks; and a multi power controller generates a signal that activates at least one of the plurality of blocks according to an address storing the instruction, and provides a normal power voltage or a reduction power voltage in response to the activation signal.

Abstract: Provided is an apparatus for controlling multiple powers which is capable of turning on and off the multiple powers in their priorities for systems or components to be supplied with the multiple powers such as a liquid crystal display (LCD) module. In the apparatus for controlling multiple powers, an on-signal of high level is applied to an input terminal, and an output of a control signal generating unit is sequentially changed to a high level whenever a clock is applied to a clock signal input terminal by one period, so that outputs of the multiple powers are sequentially output. In addition, an off signal of low level is applied to the input terminal, and an output of the control signal generating unit is changed to a low level in a reversal order whenever a clock is applied to the clock signal input terminal by one period, so that outputs of the multiple powers are interrupted in the reversal order.