Abstract: The invention implements a novel method for discarding model behaviors from the computation-tree, when these behaviors are defined by the user as ‘not interesting’. The method works as follows: the user defines, by declarative means via regular expression, a set of model behaviors that are of interest. After applying this method, referred to as the restrict algorithm henceforth, the computation-tree will consist only of paths representing model behaviors specified by the user. The restrict algorithm consists of a preprocessing stage and a processing stage. In the preprocessing stage, a mechanism for identifying when an execution path is an allowed behavior is constructed. While processing, sub-trees representing “bad behaviors” (execution paths identified as not allowed behaviors) are pruned from the computation-tree.

Abstract: A method for exploring the behavior of a design model, the method including the steps of providing a design model represented as a Finite State Machine (FSM). The method further includes the step of providing a path specification of interest. The method further includes the step of exploring the behavior of the design in order to find and present a scenario in the design that meets the path specification.

Abstract: A method of identifying peptides originating from a particular cell type and being capable of binding to MHC molecules of a particular haplotype is disclosed. The method comprises obtaining a cell type expressing a soluble and secreted form of the MHC molecules of the particular haplotype; collecting the soluble and secreted form of the MHC molecules of the particular haplotype; and analyzing peptides bound to the soluble and secreted form of the MHC molecules of the particular haplotype, thereby identifying the peptides originating from the particular cell type and being capable of binding to MHC molecules of the particular haplotype.

Abstract: A method for design verification includes receiving a software model of a design of a system under evaluation, and providing a property, which is dependent on a specified variable having a predefined range of values. The property applies to all states of the system for any selected value among the values of the variable within the predefined range. The property is processed so as to generate a checker program for detecting a violation of the property. A simulation of the system is then run using the software model together with the checker program.

Abstract: A method for verifying software source code that includes references to program variables includes processing the source code to derive a set of next-state functions representing control flow of the source code. The references to the program variables in the source code are replaced with non-deterministic choices in the next-state functions. The next-state functions including the non-deterministic choices are restricted to produce a finite-state model of the control flow. The finite-state model is then verified to find an error in the source code.

Abstract: The invention implements a novel method for discarding model behaviors from the computation-tree, when these behaviors are defined by the user as ‘not interesting’. The method works as follows: the user defines, by declarative means via regular expression, a set of model behaviors that are of interest. After applying this method, referred to as the restrict algorithm henceforth, the computation-tree will consist only of paths representing model behaviors specified by the user. The restrict algorithm consists of a preprocessing stage and a processing stage. In the preprocessing stage, a mechanism for identifying when an execution path is an allowed behavior is constructed. While processing, sub-trees representing “bad behaviors” (execution paths identified as not allowed behaviors) are pruned from the computation-tree.

Abstract: A computer-implemented method for systematically eliminating redundant circuit elements in a state machine of a model having sequential circuit elements possessing one of a fixed number of possible states, typically “0” and “1”. Initially, the sequential circuit elements are sorted into groups whose state is determinate i.e. equal to “0” or “1”. The state of each circuit element whose state is determinate is stored in memory and its next state is calculated and compared with its preceding state. Each circuit element whose successive states are different is moved to the group of indeterminate circuit elements, and the cycle is repeated in respect of all remaining determinate circuit elements until no further circuit elements are moved. Each of the remaining determinate circuit elements is then replaced by a constant equal to its corresponding state i.e. “0” or “1”.