Patents by Inventor Ilango Ganga
Ilango Ganga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 12177277Abstract: In one embodiment, a system includes a device and a host. The device includes a device stream buffer. The host includes a processor to execute at least a first application and a second application, a host stream buffer, and a host scheduler. The first application is associated with a first transmit streaming channel to stream first data from the first application to the device stream buffer. The first transmit streaming channel has a first allocated amount of buffer space in the device stream buffer. The host scheduler schedules enqueue of the first data from the first application to the first transmit streaming channel based at least in part on availability of space in the first allocated amount of buffer space in the device stream buffer. Other embodiments are described and claimed.Type: GrantFiled: May 6, 2021Date of Patent: December 24, 2024Assignee: Intel CorporationInventors: Lokpraveen Mosur, Ilango Ganga, Robert Cone, Kshitij Arun Doshi, John J. Browne, Mark Debbage, Stephen Doyle, Patrick Fleming, Doddaballapur Jayasimha
-
Publication number: 20210281618Abstract: In one embodiment, a system includes a device and a host. The device includes a device stream buffer. The host includes a processor to execute at least a first application and a second application, a host stream buffer, and a host scheduler. The first application is associated with a first transmit streaming channel to stream first data from the first application to the device stream buffer. The first transmit streaming channel has a first allocated amount of buffer space in the device stream buffer. The host scheduler schedules enqueue of the first data from the first application to the first transmit streaming channel based at least in part on availability of space in the first allocated amount of buffer space in the device stream buffer. Other embodiments are described and claimed.Type: ApplicationFiled: May 6, 2021Publication date: September 9, 2021Inventors: LOKPRAVEEN MOSUR, ILANGO GANGA, ROBERT CONE, KSHITIJ ARUN DOSHI, JOHN J. BROWNE, MARK DEBBAGE, STEPHEN DOYLE, PATRICK FLEMING, DODDABALLAPUR JAYASIMHA
-
Patent number: 11063884Abstract: This disclosure describes enhancements to Ethernet for use in higher performance applications like Storage, HPC, and Ethernet based fabric interconnects. This disclosure provides various mechanisms for lossless fabric enhancements with error-detection and retransmissions to improve link reliability, frame pre-emption to allow higher priority traffic over lower priority traffic, virtual channel support for deadlock avoidance by enhancing Class of service functionality defined in IEEE 802.1Q, a new header format for efficient forwarding/routing in the fabric interconnect and header CRC for reliable cut-through forwarding in the fabric interconnect. The enhancements described herein, when added to standard and/or proprietary Ethernet protocols, broadens the applicability of Ethernet to newer usage models and fabric interconnects that are currently served by alternate fabric technologies like Infiniband, Fibre Channel and/or other proprietary technologies, etc.Type: GrantFiled: August 28, 2019Date of Patent: July 13, 2021Assignee: Intel CorporationInventors: Ilango Ganga, Alain Gravel, Thomas Lovett, Radia Perlman, Greg Regnier, Anil Vasudevan, Hugh Wilkinson
-
Publication number: 20190386934Abstract: This disclosure describes enhancements to Ethernet for use in higher performance applications like Storage, HPC, and Ethernet based fabric interconnects. This disclosure provides various mechanisms for lossless fabric enhancements with error-detection and retransmissions to improve link reliability, frame pre-emption to allow higher priority traffic over lower priority traffic, virtual channel support for deadlock avoidance by enhancing Class of service functionality defined in IEEE 802.1Q, a new header format for efficient forwarding/routing in the fabric interconnect and header CRC for reliable cut-through forwarding in the fabric interconnect. The enhancements described herein, when added to standard and/or proprietary Ethernet protocols, broadens the applicability of Ethernet to newer usage models and fabric interconnects that are currently served by alternate fabric technologies like Infiniband, Fibre Channel and/or other proprietary technologies, etc.Type: ApplicationFiled: August 28, 2019Publication date: December 19, 2019Applicant: Intel CorporationInventors: Ilango Ganga, Alain Gravel, Thomas Lovett, Radia Perlman, Greg Regnier, Anil Vasudevan, Hugh Wilkinson
-
Patent number: 10404625Abstract: This disclosure describes enhancements to Ethernet for use in higher performance applications like Storage, HPC, and Ethernet based fabric interconnects. This disclosure provides various mechanisms for lossless fabric enhancements with error-detection and retransmissions to improve link reliability, frame pre-emption to allow higher priority traffic over lower priority traffic, virtual channel support for deadlock avoidance by enhancing Class of service functionality defined in IEEE 802.1Q, a new header format for efficient forwarding/routing in the fabric interconnect and header CRC for reliable cut-through forwarding in the fabric interconnect. The enhancements described herein, when added to standard and/or proprietary Ethernet protocols, broadens the applicability of Ethernet to newer usage models and fabric interconnects that are currently served by alternate fabric technologies like Infiniband, Fiber Channel and/or other proprietary technologies, etc.Type: GrantFiled: September 25, 2014Date of Patent: September 3, 2019Assignee: Intel CorporationInventors: Ilango Ganga, Alain Gravel, Thomas Lovett, Radia Perlman, Greg Regnier, Anil Vasudevan, Hugh Wilkinson
-
Patent number: 10205667Abstract: One embodiment provides a method for enabling class-based credit flow control for a network node in communication with a link partner using an Ethernet communications protocol. The method includes receiving a control frame from the link partner. The control frame includes at least one field for specifying credit for at least one traffic class and the credit is based on available space in a receive buffer associated with the at least one traffic class. The method further includes sending data packets to the link partner based on the credit, the data packets associated with the at least one traffic class.Type: GrantFiled: June 5, 2017Date of Patent: February 12, 2019Assignee: Intel CorporationInventors: Ilango Ganga, Alain Gravel, Thomas D. Lovett, Radia Perlman, Greg Regnier, Anil Vasudevan, Hugh Wilkinson
-
Publication number: 20170272370Abstract: One embodiment provides a method for enabling class-based credit flow control for a network node in communication with a link partner using an Ethernet communications protocol. The method includes receiving a control frame from the link partner. The control frame includes at least one field for specifying credit for at least one traffic class and the credit is based on available space in a receive buffer associated with the at least one traffic class. The method further includes sending data packets to the link partner based on the credit, the data packets associated with the at least one traffic class.Type: ApplicationFiled: June 5, 2017Publication date: September 21, 2017Applicant: Intel CorporationInventors: ILANGO GANGA, ALAIN GRAVEL, THOMAS D. LOVETT, RADIA PERLMAN, GREG REGNIER, ANIL VASUDEVAN, HUGH WILKINSON
-
Patent number: 9746899Abstract: An embodiment may include circuitry that may be capable of performing operations that may include generating, at least in part, at least one message to announce that at least one network node (1) is requesting, at least in part, that one or more transmissions to the at least one network node be postponed, at least in part, and/or (2) is entering, at least in part after issuance of the at least one message, a relatively lower power state relative to a relatively higher power state. Additionally or alternatively, the operations may include, in response, at least in part, to the at least one message, postponing, at least in part, at least one intermediate node at least one transmission (received by the at least one intermediate node) to the at least one network node. Many alternatives, variations, and/or modifications are possible without departing from this embodiment.Type: GrantFiled: March 16, 2012Date of Patent: August 29, 2017Assignee: Intel CorporationInventors: Ygdal Naouri, Ben-Zion Friedman, Eliezer Tamir, Eliel Louzoun, Ilango Ganga
-
Patent number: 9742616Abstract: Devices and techniques for indicating packet processing hints are described herein. A device may receive a data packet. The device may extract a match-action attribute from the data packet that specifies an action to be applied to the data packet. The device may generate a hint field based on the match-action attribute. The hint field may include information to be used for handling the data packet. Other embodiments are also described.Type: GrantFiled: December 23, 2014Date of Patent: August 22, 2017Assignee: Intel CorporationInventors: Nrupal Jani, Ilango Ganga, Daniel Daly, John Fastabend, Neerav Parikh, Elizabeth Kappler, Brian J. Skerry, Calin Gherghe, Sanjeev Jain, Ben-Zion Friedman
-
Patent number: 9674098Abstract: One embodiment provides a method for enabling class-based credit flow control for a network node in communication with a link partner using an Ethernet communications protocol. The method includes receiving a control frame from the link partner. The control frame includes at least one field for specifying credit for at least one traffic class and the credit is based on available space in a receive buffer associated with the at least one traffic class. The method further includes sending data packets to the link partner based on the credit, the data packets associated with the at least one traffic class.Type: GrantFiled: June 24, 2014Date of Patent: June 6, 2017Assignee: INTEL CORPORATIONInventors: Ilango Ganga, Alain Gravel, Radia Perlman, Greg Regnier, Anil Vasudevan, Hugh Wilkinson, Thomas D. Lovett
-
Patent number: 9455797Abstract: One embodiment provides a method for resolving a forward error correction (FEC) protocol. The method includes requesting, by a network node element during an auto-negotiation period between the node element and a link partner, to resolve at least one FEC mode during a link training period; wherein the auto-negotiation period and the link training period are defined by an Ethernet communications protocol and the auto-negotiation period occurs before the link training period; determining, by the network node element, at least one channel quality parameter of at least one channel of a communication link between the network node element and the link partner; and determining, by the network node element during the link training period, whether to enable at least one FEC mode for use by the network node element based on, at least in part, the at least one channel quality parameter.Type: GrantFiled: May 7, 2012Date of Patent: September 27, 2016Assignee: INTEL CORPORATIONInventors: Kent Lusted, Ilango Ganga
-
Publication number: 20160182408Abstract: Devices and techniques for indicating packet processing hints are described herein. A device may receive a data packet. The device may extract a match-action attribute from the data packet that specifies an action to be applied to the data packet. The device may generate a hint field based on the match-action attribute. The hint field may include information to be used for handling the data packet. Other embodiments are also described.Type: ApplicationFiled: December 23, 2014Publication date: June 23, 2016Inventors: Nrupal Jani, Ilango Ganga, Daniel Daly, John Fastabend, Neerav Parikh, Elizabeth Kappler, Brian J. Skerry, Calvin Gherghe, Sanjeev Jain, Ben-Zion Friedman
-
Publication number: 20150117177Abstract: This disclosure describes enhancements to Ethernet for use in higher performance applications like Storage, HPC, and Ethernet based fabric interconnects. This disclosure provides various mechanisms for lossless fabric enhancements with error-detection and retransmissions to improve link reliability, frame pre-emption to allow higher priority traffic over lower priority traffic, virtual channel support for deadlock avoidance by enhancing Class of service functionality defined in IEEE 802.1Q, a new header format for efficient forwarding/routing in the fabric interconnect and header CRC for reliable cut-through forwarding in the fabric interconnect. The enhancements described herein, when added to standard and/or proprietary Ethernet protocols, broadens the applicability of Ethernet to newer usage models and fabric interconnects that are currently served by alternate fabric technologies like Infiniband, Fibre Channel and/or other proprietary technologies, etc.Type: ApplicationFiled: September 25, 2014Publication date: April 30, 2015Inventors: Ilango Ganga, Alain Gravel, Thomas Lovett, Radia Perlman, Greg Regnier, Anil Vasudevan, Hugh Wilkinson
-
Publication number: 20150009823Abstract: One embodiment provides a method for enabling class-based credit flow control for a network node in communication with a link partner using an Ethernet communications protocol. The method includes receiving a control frame from the link partner. The control frame includes at least one field for specifying credit for at least one traffic class and the credit is based on available space in a receive buffer associated with the at least one traffic class. The method further includes sending data packets to the link partner based on the credit, the data packets associated with the at least one traffic class.Type: ApplicationFiled: June 24, 2014Publication date: January 8, 2015Inventors: Ilango Ganga, Alain Gravel, Anil Vasudevan, Radia Perlman, Greg Regnier, Anil Vasudevan, Hugh Wilkinson
-
Publication number: 20140223265Abstract: One embodiment provides a method for resolving a forward error correction (FEC) protocol. The method includes requesting, by a network node element during an auto-negotiation period between the node element and a link partner, to resolve at least one FEC mode during a link training period; wherein the auto-negotiation period and the link training period are defined by an Ethernet communications protocol and the auto-negotiation period occurs before the link training period; determining, by the network node element, at least one channel quality parameter of at least one channel of a communication link between the network node element and the link partner; and determining, by the network node element during the link training period, whether to enable at least one FEC mode for use by the network node element based on, at least in part, the at least one channel quality parameter.Type: ApplicationFiled: May 7, 2012Publication date: August 7, 2014Inventors: Kent Lusted, Ilango Ganga
-
Patent number: 8661313Abstract: Techniques are described that can extend the transmission rate over cable. Multiple cables can be used to increase the transmission rate. The transmission standard applied for each cable can be an Ethernet backplane standard such as IEEE 802.3ap (2007). Data can be assigned to virtual lanes prior to transmission over a cable. Forward error correction may be applied to each virtual lane prior to transmission over cable. Forward error correction may be negotiated over a single virtual lane and then applied to all virtual lanes.Type: GrantFiled: December 28, 2012Date of Patent: February 25, 2014Assignee: Intel CorporationInventors: Ilango Ganga, Richard Mellitz
-
Patent number: 8645804Abstract: Techniques are described that can be used to extend the data transmission rate specified by 10GBASE-KR of IEEE 802.3ap (2007) to more than 10 Gb/s using a multiple lane backplane. A signal for transmission over 10 Gb/s can be divided into multiple streams for transmission over multiple lanes. Multiple transceiver pairs can be used for transmission and receipt of the multiple streams. Each transceiver pair may comply with 10GBASE-KR of IEEE 802.3ap (2007).Type: GrantFiled: October 8, 2012Date of Patent: February 4, 2014Assignee: Intel CorporationInventors: Ilango Ganga, Richard Mellitz
-
Publication number: 20130246828Abstract: An embodiment may include circuitry that may be capable of performing operations that may include generating, at least in part, at least one message to announce that at least one network node (1) is requesting, at least in part, that one or more transmissions to the at least one network node be postponed, at least in part, and/or (2) is entering, at least in part after issuance of the at least one message, a relatively lower power state relative to a relatively higher power state. Additionally or alternatively, the operations may include, in response, at least in part, to the at least one message, postponing, at least in part, at least one intermediate node at least one transmission (received by the at least one intermediate node) to the at least one network node. Many alternatives, variations, and/or modifications are possible without departing from this embodiment.Type: ApplicationFiled: March 16, 2012Publication date: September 19, 2013Inventors: Ygdal Naouri, Ben-Zion Friedman, Eliezer Tamir, Eliel Louzoun, Ilango Ganga
-
Publication number: 20130117639Abstract: Techniques are described that can extend the transmission rate over cable. Multiple cables can be used to increase the transmission rate. The transmission standard applied for each cable can be an Ethernet backplane standard such as IEEE 802.3ap (2007). Data can be assigned to virtual lanes prior to transmission over a cable. Forward error correction may be applied to each virtual lane prior to transmission over cable. Forward error correction may be negotiated over a single virtual lane and then applied to all virtual lanes.Type: ApplicationFiled: December 28, 2012Publication date: May 9, 2013Inventors: Ilango Ganga, Richard Mellitz
-
Publication number: 20130031445Abstract: Techniques are described that can be used to extend the data transmission rate specified by 10GBASE-KR of IEEE 802.3ap (2007) to more than 10 Gb/s using a multiple lane backplane. A signal for transmission over 10 Gb/s can be divided into multiple streams for transmission over multiple lanes. Multiple transceiver pairs can be used for transmission and receipt of the multiple streams. Each transceiver pair may comply with 10GBASE-KR of IEEE 802.3ap (2007).Type: ApplicationFiled: October 8, 2012Publication date: January 31, 2013Inventors: Ilango Ganga, Richard Mellitz