Abstract: A method of operating a computing device includes performing a pre-boot memory test on a memory by a BIOS (Basic Input/Output System), recording, in a log, memory fail information generated as a result of performing the pre-boot memory test by the BIOS, and performing a page offline operation using the memory fail information, after an operating system (OS) of the computing device is installed.

Abstract: A method of operating a computing device includes performing a pre-boot memory test on a memory by a BIOS (Basic Input/Output System), recording, in a log, memory fail information generated as a result of performing the pre-boot memory test by the BIOS, and performing a page offline operation using the memory fail information, after an operating system (OS) of the computing device is installed.

Abstract: A semiconductor package includes a chip stack having a plurality of semiconductor chips vertically stacked on a package substrate. A stress-equalizing chip is disposed on the chip stack, the stress-equalizing chip providing means to reduce the variation in the electrical characteristics of the plurality of semiconductor chips. An encapsulant is disposed on the package substrate and is configured to cover at least a portion of the chip stack. Each of the plurality of semiconductor chips is electrically connected to the package substrate. The stress-equalizing chip is not electrically connected to the substrate or to the plurality of semiconductor chips.

Abstract: A semiconductor package includes a chip stack having a plurality of semiconductor chips vertically stacked on a package substrate. A stress-equalizing chip is disposed on the chip stack, the stress-equalizing chip providing means to reduce the variation in the electrical characteristics of the plurality of semiconductor chips. An encapsulant is disposed on the package substrate and is configured to cover at least a portion of the chip stack. Each of the plurality of semiconductor chips is electrically connected to the package substrate. The stress-equalizing chip is not electrically connected to the substrate or to the plurality of semiconductor chips.

Abstract: Provided are a transparent display device and a method for controlling same. This transparent display device comprises: a sensor which measures the color properties of light that is incident to the transparent display device; a light control unit which is configured so as to control the amount of light that is incident to the rear surface of the transparent display unit and penetrates a plurality of penetration units; and a transparent display panel which comprises a control unit configured so as to correct color distortion by making a comparison with a preset threshold value on the basis of the measured color properties and correcting the image to be displayed on a plurality of pixels, the transparent display panel displaying the corrected input image.

Abstract: Provided are a transparent display device and a method for controlling same. This transparent display device comprises: a sensor which measures the colour properties of light that is incident to the transparent display device; a light control unit which is configured so as to control the amount of light that is incident to the rear surface of the transparent display unit and penetrates a plurality of penetration units; and a transparent display panel which comprises a control unit configured so as to correct colour distortion by making a comparison with a preset threshold value on the basis of the measured colour properties and correcting the image to be displayed on a plurality of pixels, the transparent display panel displaying the corrected input image.

Abstract: A display device includes a plurality of gate lines and a plurality of data lines crossing each other on a first substrate, to define a pixel; a first thin film transistor in a portion where the gate lines and the data lines cross each other; a plurality of position detection lines on the first substrate, the position detection lines spaced a constant distance from the data lines and crossing the gate lines; a second thin film transistor for detecting a position, in a portion on the first substrate where the gate lines and the position detection lines cross each other; a protrusion pattern protruding from a second substrate and corresponding to a drain electrode of the second thin film transistor; and a transparent conductive layer on the protrusion pattern, electrically connected to the drain electrode when touching.

Abstract: An image quality analysis method and an image quality analysis system for a display device are provided. The image quality analysis method and image quality analysis system provides a quantitative determination of image quality for display devices, thereby providing an objective and fair evaluation criterion.

Abstract: An image quality analysis method and an image quality analysis system for a display device are provided. The image quality analysis method and image quality analysis system provides a quantitative determination of image quality for display devices, thereby providing an objective and fair evaluation criterion.