Abstract: An embodiment armrest assembly for a vehicle includes an armrest including a main body and a lid, an armrest board to which the armrest is rotatably coupled and in which the armrest is accommodated in an erect state, and a skirt coupled to a rear bezel housing of the lid and to the armrest board and correspondingly covering a rear space of the lid when the armrest is rotated forward, wherein the skirt has a panel shape and includes a hard material.

Abstract: Disclosed are an arc extinguishing unit, a circuit breaking unit, and an air circuit breaker including the same. The present disclosure provides an arc extinguishing unit, a circuit breaking unit, and an air circuit breaker, including: side plates spaced apart from each other and disposed to face each other; a plurality of grids disposed between the side plates, spaced apart from each other, and coupled to the side plates, respectively; and a grid cover located above the grid and covering the grid, wherein the grid includes a grid leg extending downward to surround from both sides a protruding contact disposed to extend upward from a movable contact; and a first protective part formed to surround at least a portion of the grid leg at a lower portion of the grid leg.

Abstract: An embodiment armrest assembly for a vehicle includes an armrest rotatably coupled to an armrest board and configured to be extended from the armrest board by rotating forward or to be housed in the armrest board by rotating and standing and a speed-reduction damper mechanism connecting the armrest and the armrest board and configured to make a rotational speed of the armrest uniform by reducing the rotational speed when the armrest rotates to be extended.

Abstract: A vertical semiconductor device and a method for fabricating the same may include forming an alternating stack of dielectric layers and sacrificial layers over a lower structure, forming an opening by etching the alternating stack, forming a non-conformal blocking layer on the alternating stack in which the opening is formed, adsorbing a deposition inhibitor on a surface of the blocking layer to convert the non-conformal blocking layer into a conformal blocking layer on which the deposition inhibitor is adsorbed, and forming a charge storage layer on the conformal blocking layer.

Abstract: According to one aspect of the present invention, it is possible to provide a tailor welded blank, a hot press formed part, and a method for manufacturing same, the tailor welded blank having a weld part that can effectively prevent deterioration of properties after hot press forming.

Abstract: A touch detection module, includes: a plurality of driving electrodes arranged side by side; a plurality of sensing electrodes staggered with respect to the driving electrodes; and a touch driving circuit configured to supply touch driving signals to the plurality of driving electrodes and to detect touch detection signals through the plurality of sensing electrodes to identify touch position coordinates, wherein the touch driving circuit is configured: to vary frequency modulation parameter set values in response to a change in a frequency of reference clocks, and to generate and supply a frequency of the touch driving signals by using the reference clocks and a varied frequency modulation parameter set value.

Abstract: A power source switching circuit for a memory device includes: a first power source voltage terminal for supplying a first power source voltage, a second power source voltage terminal for supplying a second power source voltage, a first metal-oxide-semiconductor field-effect transistor (MOSFET) and a second MOSFET connected in series with the first power source voltage terminal, a first level shifter connected to the first MOSFET and supplied with the first power source voltage, a second level shifter connected to the second MOSFET and supplied with the second power source voltage, a third MOSFET connected to the second MOSFET, and a third level shifter connected to the third MOSFET and supplied with a third power source voltage, and a memory cell of a non-volatile memory is programmed using the first power source voltage or the second power source voltage.

Abstract: A method of a first terminal may include: identifying first RB set(s) to be used for SL communication among consecutive RB sets through an LBT procedure; identifying a first subchannel group included in the first RB set(s) and a second subchannel group including a first PRB in the first RB set(s), the first PRB being not included in the first subchannel group; configuring the first PRB within the second subchannel group as an SL communication resource; and transmitting, to a second terminal, control information indicating that the first PRB is configured as the SL communication resource.

Abstract: A semiconductor device includes an active pattern including: a lower pattern extending in a first direction, and a plurality of sheet patterns spaced apart from the lower pattern in a second direction; a gate structure on the lower pattern and including a gate electrode and a gate insulating film including an interfacial insulating film including a first vertical portion and a horizontal portion. A dimension in a third direction of the first vertical portion is greater than a dimension in the second direction of the horizontal portion. The first vertical portion includes: a first area contacting a source/drain pattern; and a second area provided between the first area and the gate electrode. The interfacial insulating film includes a first element other than silicon, wherein a concentration of the first element in the first area is greater than a concentration of the first element in the second area.

Abstract: An airbag maintains deployment performance of an airbag cushion installed in a structure for dividing an occupant compartment space. The airbag includes an airbag cushion that includes a plurality of deployment areas and a spacing part that is disposed at a position adjacent to the plurality of deployment areas and separates the plurality of deployment area from one another.

Abstract: An electronic device including a memory device with improved reliability is provided. The semiconductor device comprises a data pin configured to transmit a data signal, a command/address pin configured to transmit a command and an address, a command/address receiver connected to the command/address pin, and a computing unit connected to the command/address receiver, wherein the command/address receiver receives a first command and a first address from the outside through the command/address pin and generates a first instruction on the basis of the first command and the first address, and the computing unit receives the first instruction and performs computation based on the first instruction.

Abstract: A heat sink plate includes a first layer made of copper (Cu) or a copper (Cu) alloy, a second layer formed on the first layer and made of molybdenum (Mo) or an alloy that includes copper (Cu) and one or more components selected from molybdenum (Mo), tungsten (W), carbon (C), chromium (Cr), titanium (Ti), and beryllium (Be), a third layer formed on the second layer and made of copper (Cu) or a copper (Cu) alloy, a fourth layer formed on the third layer and made of molybdenum (Mo) or an alloy that includes copper (Cu) and one or more components selected from molybdenum (Mo), tungsten (W), carbon (C), chromium (Cr), titanium (Ti), and beryllium (Be), and a fifth layer formed on the fourth layer and made of copper (Cu) or a copper (Cu) alloy.

Abstract: A semiconductor package includes a chip stack having a plurality of semiconductor chips vertically stacked on a package substrate. A stress-equalizing chip is disposed on the chip stack, the stress-equalizing chip providing means to reduce the variation in the electrical characteristics of the plurality of semiconductor chips. An encapsulant is disposed on the package substrate and is configured to cover at least a portion of the chip stack. Each of the plurality of semiconductor chips is electrically connected to the package substrate. The stress-equalizing chip is not electrically connected to the substrate or to the plurality of semiconductor chips.

Abstract: A heat sink plate includes a first layer made of copper (Cu) or a copper (Cu) alloy, a second layer formed on the first layer and made of molybdenum (Mo) or an alloy that includes copper (Cu) and one or more components selected from molybdenum (Mo), tungsten (W), carbon (C), chromium (Cr), titanium (Ti), and beryllium (Be), a third layer formed on the second layer and made of copper (Cu) or a copper (Cu) alloy, a fourth layer formed on the third layer and made of molybdenum (Mo) or an alloy that includes copper (Cu) and one or more components selected from molybdenum (Mo), tungsten (W), carbon (C), chromium (Cr), titanium (Ti), and beryllium (Be), and a fifth layer formed on the fourth layer and made of copper (Cu) or a copper (Cu) alloy.

Abstract: A heat sink plate having a structure in which two or more kinds of materials are laminated, includes: a core layer in the thickness direction of the heat sink plate; and cover layers covering a top surface and a bottom surface of the core layer; wherein the cover layers comprise a material containing copper, wherein the core layer is formed of a matrix having a first thermal expansion coefficient and a plurality of layers extending in parallel along the thickness direction of the core layer in a lattice form in the matrix, wherein the plurality of layers are made of an alloy having a second thermal expansion coefficient.

Abstract: A semiconductor package includes a chip stack having a plurality of semiconductor chips vertically stacked on a package substrate. A stress-equalizing chip is disposed on the chip stack, the stress-equalizing chip providing means to reduce the variation in the electrical characteristics of the plurality of semiconductor chips. An encapsulant is disposed on the package substrate and is configured to cover at least a portion of the chip stack. Each of the plurality of semiconductor chips is electrically connected to the package substrate. The stress-equalizing chip is not electrically connected to the substrate or to the plurality of semiconductor chips.