Patents by Inventor Ilija Dukovski

Ilija Dukovski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040266045
    Abstract: A method is for making a semiconductor device by forming a superlattice that, in turn, includes a plurality of stacked groups of layers. The method may also include forming regions for causing transport of charge carriers through the superlattice in a parallel direction relative to the stacked groups of layers. Each group of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions so that the superlattice may have a higher charge carrier mobility in the parallel direction than would otherwise occur. The superlattice may also have a common energy band structure therein.
    Type: Application
    Filed: August 22, 2003
    Publication date: December 30, 2004
    Applicant: RJ Mears LLC.
    Inventors: Robert J. Mears, Jean Augustin Chan Sow Fook Yiptong, Marek Hytha, Scott A. Kreps, Ilija Dukovski
  • Publication number: 20040262597
    Abstract: A semiconductor device includes a substrate, and at least one MOSFET adjacent the substrate. The MOSFET may include a superlattice channel that, in turn, includes a plurality of stacked groups of layers. The MOSFET may also include source and drain regions laterally adjacent the superlattice channel, and a gate overlying the superlattice channel for causing transport of charge carriers through the superlattice channel in a parallel direction relative to the stacked groups of layers. Each group of the superlattice channel may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and an energy band-modifying layer thereon. The energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions so that the superlattice channel may have a higher charge carrier mobility in the parallel direction than would otherwise occur.
    Type: Application
    Filed: August 22, 2003
    Publication date: December 30, 2004
    Applicant: RJ Mears, LLC
    Inventors: Robert J. Mears, Jean Augustin Chan Sow Fook Yiptong, Marek Hytha, Scott A. Kreps, Ilija Dukovski
  • Publication number: 20040262595
    Abstract: A semiconductor device includes a superlattice that, in turn, includes a plurality of stacked groups of layers. The device may also include regions for causing transport of charge carriers through the superlattice in a parallel direction relative to the stacked groups of layers. Each group of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. Moreover, the energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Accordingly, the superlattice may have a higher charge carrier mobility in the parallel direction than would otherwise be present.
    Type: Application
    Filed: August 22, 2003
    Publication date: December 30, 2004
    Applicant: RJ Mears LLC
    Inventors: Robert J. Mears, Jean Augustin Chan Sow Fook Yiptong, Marek Hytha, Scott A. Kreps, Ilija Dukovski
  • Publication number: 20040262594
    Abstract: The present invention relates to controlling the properties of semiconductor materials at the atomic or molecular level to achieve improved performance within semiconductor devices. Further, the invention relates to the identification, creation, and use of improved materials for use in the conduction paths of semiconductor devices. More specifically, the inventors have identified materials or structures having energy band structures in which the average curvature of the conduction and valence bands and band edges is substantially greater than the average curvature of conduction and valence bands in single crystal silicon. This substantially greater curvature corresponds to lower effective mass and, hence, greater carrier mobility.
    Type: Application
    Filed: June 26, 2003
    Publication date: December 30, 2004
    Applicant: RJ Mears, LLC
    Inventors: Robert J. Mears, Jean Augustin Chan Sow Fook Yiptong, Marek Hytha, Ilija Dukovski
  • Publication number: 20040262628
    Abstract: A semiconductor device includes a superlattice that, in turn, includes a plurality of stacked groups of layers. The device may also include regions for causing transport of charge carriers through the superlattice in a parallel direction relative to the stacked groups of layers. Each group of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. Moreover, the energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Accordingly, the superlattice may have a higher charge carrier mobility in the parallel direction than would otherwise be present.
    Type: Application
    Filed: November 19, 2003
    Publication date: December 30, 2004
    Applicant: RJ Mears, LLC
    Inventors: Robert J. Mears, Jean Augustin Chan Sow Fook Yiptong, Marek Hytha, Scott A. Kreps, Ilija Dukovski
  • Publication number: 20040262596
    Abstract: A semiconductor device includes a superlattice that, in turn, includes a plurality of stacked groups of layers. The device may also include regions for causing transport of charge carriers through the superlattice in a parallel direction relative to the stacked groups of layers. Each group of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. Moreover, the energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Accordingly, the superlattice may have a higher charge carrier mobility in the parallel direction than would otherwise be present.
    Type: Application
    Filed: November 19, 2003
    Publication date: December 30, 2004
    Applicant: RJ Mears, LLC.
    Inventors: Robert J. Mears, Jean Augustin Chan Sow Fook Yiptong, Marek Hytha, Scott A. Kreps, Ilija Dukovski
  • Publication number: 20040261695
    Abstract: A method is for making a semiconductor device by forming a superlattice that, in turn, includes a plurality of stacked groups of layers. The method may also include forming regions for causing transport of charge carriers through the superlattice in a parallel direction relative to the stacked groups of layers. Each group of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions so that the superlattice may have a higher charge carrier mobility in the parallel direction than would otherwise occur. The superlattice may also have a common energy band structure therein.
    Type: Application
    Filed: November 19, 2003
    Publication date: December 30, 2004
    Applicant: RJ Mears, LLC.
    Inventors: Robert J. Mears, Jean Augustin Chan Sow Fook Yiptong, Marek Hytha, Scott A. Kreps, Ilija Dukovski
  • Patent number: 6833294
    Abstract: A method is for making a semiconductor device by forming a superlattice that, in turn, includes a plurality of stacked groups of layers. The method may also include forming regions for causing transport of charge carriers through the superlattice in a parallel direction relative to the stacked groups of layers. Each group of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions so that the superlattice may have a higher charge carrier mobility in the parallel direction than would otherwise occur. The superlattice may also have a common energy band structure therein.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: December 21, 2004
    Assignee: RJ Mears, LLC
    Inventors: Robert J. Mears, Jean Augustin Chan Sow Fook Yiptong, Marek Hytha, Scott A. Kreps, Ilija Dukovski
  • Patent number: 6830964
    Abstract: A method is for making a semiconductor device by forming a superlattice that, in turn, includes a plurality of stacked groups of layers. The method may also include forming regions for causing transport of charge carriers through the superlattice in a parallel direction relative to the stacked groups of layers. Each group of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions so that the superlattice may have a higher charge carrier mobility in the parallel direction than would otherwise occur. The superlattice may also have a common energy band structure therein.
    Type: Grant
    Filed: August 22, 2003
    Date of Patent: December 14, 2004
    Assignee: RJ Mears, LLC
    Inventors: Robert J. Mears, Jean Augustin Chan Sow Fook Yiptong, Marek Hytha, Scott A. Kreps, Ilija Dukovski