Patents by Inventor Ilya Alexandrovich

Ilya Alexandrovich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200188926
    Abstract: The invention relates to means for the autogenous grinding, separation and drying of various solid materials in a continuous process and can be used in many branches of industry. The technical result consists in creating a high-speed, powerful and at the same time energy-efficient, simple and reliable device and method for breaking up an initial stock and simultaneously drying particles of the ground stock. The technical result is achieved by feeding an initial stock into a grinding working area, grinding the initial stock and drying particles of the ground initial stock and discharging the ground and to a certain extent the dried particles of the initial stock outwards, with the initial stock being fed in and the dried particles of the ground stock being discharged by rotation of working flywheels.
    Type: Application
    Filed: November 14, 2017
    Publication date: June 18, 2020
    Inventor: Ilya Alexandrovich SEMIN
  • Patent number: 10664179
    Abstract: An integrated circuit includes protected container access control logic to perform a set of access control checks and to determine whether to allow a device protected container module (DPCM) and an input and/or output (I/O) device to communicate securely through one of direct memory access (DMA) and memory-mapped input/output (MMIO). The DPCM and the I/O device are allowed to communicate securely if it is determined that at least the DPCM and the I/O device are mapped to one another, an access address associated with the communication resolves into a protected container memory, and a page of the protected container memory into which the access address resolves allows for the aforementioned one of DMA and MMIO. In some cases, a Security Attributes of Initiator (SAI) or security identifier may be used to obtain a DPCM identifier or attest that access is from a DPCM mapped to the I/O device.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Ilya Alexandrovich, Vladimir Beker, Gideon Gerzon, Vincent R. Scarlata
  • Publication number: 20200142838
    Abstract: A processor includes a decode unit to decode an instruction that is to indicate a page of a protected container memory, and a storage location outside of the protected container memory. An execution unit, in response to the instruction, is to ensure that there are no writable references to the page of the protected container memory while it has a write protected state. The execution unit is to encrypt a copy of the page of the protected container memory. The execution unit is to store the encrypted copy of the page to the storage location outside of the protected container memory, after it has been ensured that there are no writable references. The execution unit is to leave the page of the protected container memory in the write protected state, which is also valid and readable, after the encrypted copy has been stored to the storage location.
    Type: Application
    Filed: December 27, 2019
    Publication date: May 7, 2020
    Inventors: Carlos V. Rozas, Mona Vij, Rebekah M. Leslie-Hurd, Krystof C. Zmudzinski, Somnath Chakrabarti, Francis X. Mckeen, Vincent R. Scarlata, Simon P. Johnson, Ilya Alexandrovich, Gilbert Neiger, Vedvyas Shanbhogue, Ittai Anati
  • Patent number: 10628315
    Abstract: Secure memory repartitioning technologies are described. Embodiments of the disclosure may include a processing device including a processing core and a memory controller coupled between the processor core and a memory device. The memory device includes a memory range including a section of convertible pages that are convertible to secure pages or non-secure pages. The processor core is to receive a non-secure access request to a page in the memory device, responsive to a determination, based on one or more secure state bits in one or more secure state bit arrays, that the page is a secure page, insert an abort page address into a translation lookaside buffer, and responsive to a determination, based on the one or more secure state bits in the one or more secure state bit arrays, that the page is a non-secure page, insert the page into the translation lookaside buffer.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: April 21, 2020
    Assignee: Intel Corporation
    Inventors: Vedvyas Shanbhogue, Krystof C. Zmudzinski, Carlos V. Rozas, Francis X. McKeen, Raghunandan Makaram, Ilya Alexandrovich, Ittai Anati, Meltem Ozsoy
  • Patent number: 10614036
    Abstract: Techniques have been provided for storing data in a de-duplicated manner on a data storage system in a manner that allows for real-time reference to an index that is too large to fit within memory. This may be accomplished by segmenting the index into smaller segments, stored on disk. Only a subset of the segments may be loaded into memory at a given time. A predictive filter is stored in memory for each segment, allowing a de-duplication driver to quickly predict whether any given new block is likely to be indexed by each segment. Since identical blocks are often stored in long identical sequences (e.g., upon copying a disk image to a disk for a virtual machine), once a segment stored on disk is referenced many times in a short period, it is loaded into memory to allow the remainder of the long sequence to be de-duplicated.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: April 7, 2020
    Assignee: AMC IP Holding Company LLC
    Inventors: Ilya Usvyatsky, Nickolay Alexandrovich Dalmatov
  • Patent number: 10592107
    Abstract: Embodiments are directed to a method performed by a computing device. The method includes (a) receiving, by the computing device, a stream of storage management commands directed at logical disks hosted by a DSS, the logical disks being accessible to VMs running on a remote host, each storage management command having a command type of a plurality of command types, each command type of the plurality of command types having a respective timeout period, (b) placing the storage management commands of the stream into a VM storage management queue stored on the computing device, and (c) selectively dequeueing storage management commands stored in the VM storage management queue to be performed by the DSS, wherein selectively dequeueing includes applying a set of dequeueing criteria, the set of dequeueing criteria including a criterion that selects storage management commands from the VM storage management queue according to their respective command types.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: March 17, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Sergey Alexandrovich Alexeev, Alexey Vladimirovich Shusharin, Ilya Konstantinovich Morev, Sergey Alexandrovich Zaporozhtsev, Yakov Stanislavovich Belikov
  • Patent number: 10592421
    Abstract: Instructions and logic provide advanced paging capabilities for secure enclave page caches. Embodiments include multiple hardware threads or processing cores, a cache to store secure data for a shared page address allocated to a secure enclave accessible by the hardware threads. A decode stage decodes a first instruction specifying said shared page address as an operand, and execution units mark an entry corresponding to an enclave page cache mapping for the shared page address to block creation of a new translation for either of said first or second hardware threads to access the shared page. A second instruction is decoded for execution, the second instruction specifying said secure enclave as an operand, and execution units record hardware threads currently accessing secure data in the enclave page cache corresponding to the secure enclave, and decrement the recorded number of hardware threads when any of the hardware threads exits the secure enclave.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: March 17, 2020
    Assignee: Intel Corporation
    Inventors: Carlos V. Rozas, Ilya Alexandrovich, Ittai Anati, Alex Berenzon, Michael A. Goldsmith, Barry E. Huntley, Anton Ivanov, Simon P. Johnson, Rebekah M. Leslie-Hurd, Francis X. McKeen, Gilbert Neiger, Rinat Rappoport, Scott D. Rodgers, Uday R. Savagaonkar, Vincent R. Scarlata, Vedvyas Shanbhogue, Wesley H. Smith, William C. Wood
  • Patent number: 10558588
    Abstract: A processor includes a decode unit to decode an instruction that is to indicate a page of a protected container memory, and a storage location outside of the protected container memory. An execution unit, in response to the instruction, is to ensure that there are no writable references to the page of the protected container memory while it has a write protected state. The execution unit is to encrypt a copy of the page of the protected container memory. The execution unit is to store the encrypted copy of the page to the storage location outside of the protected container memory, after it has been ensured that there are no writable references. The execution unit is to leave the page of the protected container memory in the write protected state, which is also valid and readable, after the encrypted copy has been stored to the storage location.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: February 11, 2020
    Assignee: Intel Corporation
    Inventors: Carlos V. Rozas, Mona Vij, Rebekah M. Leslie-Hurd, Krystof C. Zmudzinski, Somnath Chakrabarti, Francis X. Mckeen, Vincent R. Scarlata, Simon P. Johnson, Ilya Alexandrovich, Gilbert Neiger, Vedvyas Shanbhogue, Ittai Anati
  • Patent number: 10552344
    Abstract: A secure enclave circuit stores an enclave page cache map to track contents of a secure enclave in system memory that stores secure data containing a page having a virtual address. An execution unit is to, in response to a request to evict the page from the secure enclave: block creation of translations of the virtual address; record one or more hardware threads currently accessing the secure data in the secure enclave; send an inter-processor interrupt to one or more cores associated with the one or more hardware threads, to cause the one or more hardware threads to exit the secure enclave and to flush translation lookaside buffers of the one or more cores; and in response to detection of a page fault associated with the virtual address for the page in the secure enclave, unblock the creation of translations of the virtual address.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: February 4, 2020
    Assignee: Intel Corporation
    Inventors: Carlos V. Rozas, Ittai Anati, Francis X. McKeen, Krystof Zmudzinski, Ilya Alexandrovich, Somnath Chakrabarti, Dror Caspi, Meltem Ozsoy
  • Patent number: 10534724
    Abstract: Instructions and logic support suspending and resuming migration of enclaves in a secure enclave page cache (EPC). An EPC stores a secure domain control structure (SDCS) in storage accessible by an enclave for a management process, and by a domain of enclaves. A second processor checks if a corresponding version array (VA) page is bound to the SDCS, and if so: increments a version counter in the SDCS for the page, performs an authenticated encryption of the page from the EPC using the version counter in the SDCS, and writes the encrypted page to external memory. A second processor checks if a corresponding VA page is bound to a second SDCS of the second processor, and if so: performs an authenticated decryption of the page using a version counter in the second SDCS, and loads the decrypted page to the EPC in the second processor if authentication passes.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: January 14, 2020
    Assignee: Intel Corporation
    Inventors: Carlos V. Rozas, Ilya Alexandrovich, Gilbert Neiger, Francis X. McKeen, Ittai Anati, Vedvyas Shanbhogue, Mona Vij, Rebekah Leslie-Hurd, Krystof C. Zmudzinski, Somnath Chakrabarti, Vincent R. Scarlata, Simon P. Johnson
  • Patent number: 10470064
    Abstract: User Equipment (UE) and base station (eNB) apparatus and methodology for radio resource management reporting. The UE receives reference signals from at least one antenna port of an eNB via a plurality of receive antennas of the UE. The UE performs received signal measurement of at least a portion of the reference signals for a plurality of eNB antenna port and UE receive antenna combinational groupings to produce enhanced received signal quality (eRSQ) measurements that represent spatial characteristics of the reference signaling as received by the UE. The UE may send a report to the eNB based on the eRSQ measurements, with the report being indicative of spatial multiplexing layer availability of the UE to be served by the eNB.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: November 5, 2019
    Assignee: Intel Corporation
    Inventors: Alexei Vladimirovich Davydov, Ilya Bolotin, Alexander Alexandrovich Maltsev, Jr., Gregory Vladimirovich Morozov, Vadim Sergeyevich Sergeyev
  • Publication number: 20190324918
    Abstract: A processor for supporting secure memory intent is disclosed. The processor of the disclosure includes a memory execution unit to access memory and a processor core coupled to the memory execution unit. The processor core is to receive a request to access a convertible page of the memory. In response to the request, the processor core to determine an intent for the convertible page in view of a page table entry (PTE) corresponding to the convertible page. The intent indicates whether the convertible page is to be accessed as at least one of a secure page or a non-secure page.
    Type: Application
    Filed: May 3, 2019
    Publication date: October 24, 2019
    Inventors: Krystof C. Zmudzinski, Siddhartha Chhabra, Uday R. Savagaonkar, Simon P. Johnson, Rebekah M. Leslie-Hurd, Francis X. McKeen, Gilbert Neiger, Raghunandan Makaram, Carlos V. Rozas, Amy L. Santoni, Vincent R. Scarlata, Vedvyas Shanbhogue, Ilya Alexandrovich, Ittai Anati, Wesley H. Smith, Michael Goldsmith
  • Patent number: 10443494
    Abstract: A system and related method for providing a highly reactive fuel to a combustor of a gas turbine are disclosed herein. The system includes a fuel supply system that is in fluid communication with a fuel supply. The fuel supply system includes multiple fuel circuits. Each fuel circuit individually feeds fuel to a corresponding fuel distribution manifold. The system further includes a steam injection system. The steam injection system includes at least one flow control valve that is in fluid communication with at least one of the fuel circuits. The flow control valve provides for fluid communication between a superheated steam source and the fuel circuit during both fueled operation and during non-fueled operation of the corresponding fuel circuit.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: October 15, 2019
    Assignee: General Electric Company
    Inventors: Douglas Frank Beadie, Ilya Alexandrovich Slobodyanskiy, Jeffrey Scott Goldmeer
  • Patent number: 10409597
    Abstract: Embodiments of an invention for memory management in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive a first instruction and a second instruction. The execution unit is to execute the first instruction, wherein execution of the first instruction includes allocating a page in an enclave page cache to a secure enclave. The execution unit is also to execute the second instruction, wherein execution of the second instruction includes confirming the allocation of the page.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: September 10, 2019
    Assignee: Intel Corporation
    Inventors: Rebekah Leslie-Hurd, Carlos V. Rozas, Vincent R. Scarlata, Simon P. Johnson, Uday R. Savagaonkar, Barry E. Huntley, Vedvyas Shanbhogue, Ittai Anati, Francis X. Mckeen, Michael A. Goldsmith, Ilya Alexandrovich, Alex Berenzon, Wesley H. Smith, Gilbert Neiger
  • Publication number: 20190269824
    Abstract: The present invention relates to the field of pharmaceutics and medicine, in particular, to a method for producing a suspended form of ground decellularized extracellular matrix with size-controlled structural components, the suspended form not 5 requiring pre-hydration, and to a product produced by this method, for stimulation of reparative regeneration of tissues.
    Type: Application
    Filed: October 23, 2017
    Publication date: September 5, 2019
    Applicant: LIMITED LIABILITY COMPANY "NEARMEDIC PLUS"
    Inventors: Ashot Agabegovich SAFOYAN, Anatoly Petrvich SUSLOV, Vladimir Georgievich NESTERENKO, Sergei Vladimirovich NESTERENKO, Nina Vladimirovna KALMYKOVA, Ilya Alexandrovich DEMYANENKO, Oleg Vladimirovich SOROKIN
  • Patent number: 10338957
    Abstract: A secure migration enclave is provided to identify a launch of a particular virtual machine on a host computing system, where the particular virtual machine is launched to include a secure quoting enclave to perform an attestation of one or more aspects of the virtual machine. A root key for the particular virtual machine is generated using the secure migration enclave hosted on the host computing system for use in association with provisioning the secure quoting enclave with an attestation key to be used in the attestation. The migration enclave registers the root key with a virtual machine registration service.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: July 2, 2019
    Assignee: Intel Corporation
    Inventors: Vincent R. Scarlata, Carlos V. Rozas, Simon P. Johnson, Francis X. McKeen, Mona Vij, Somnath Chakrabarti, Brandon Baker, Ittai Anati, Ilya Alexandrovich
  • Publication number: 20190196982
    Abstract: A secure enclave circuit stores an enclave page cache map to track contents of a secure enclave in system memory that stores secure data containing a page having a virtual address. An execution unit is to, in response to a request to evict the page from the secure enclave: block creation of translations of the virtual address; record one or more hardware threads currently accessing the secure data in the secure enclave; send an inter-processor interrupt to one or more cores associated with the one or more hardware threads, to cause the one or more hardware threads to exit the secure enclave and to flush translation lookaside buffers of the one or more cores; and in response to detection of a page fault associated with the virtual address for the page in the secure enclave, unblock the creation of translations of the virtual address.
    Type: Application
    Filed: December 26, 2017
    Publication date: June 27, 2019
    Inventors: Carlos V. ROZAS, Ittai ANATI, Francis X. MCKEEN, Krystof ZMUDZINSKI, Ilya ALEXANDROVICH, Somnath CHAKRABARTI, Dror CASPI, Meltem OZSOY
  • Patent number: 10324862
    Abstract: Implementations of the disclosure provide for supporting oversubscription of guest enclave memory pages. In one implementation, a processing device comprising a memory controller unit to access a secure enclave and a processor core, operatively coupled to the memory controller unit. The processing device is to identify a target memory page in memory. The target memory page is associated with a secure enclave of a virtual machine (VM). A data structure comprising context information corresponding to the target memory page is received. A state of the target memory page is determined based on the received data structure. The state indicating whether the target memory page is associated with at least one of: a child memory page or a parent memory page of the VM. Thereupon, an instruction to evict the target memory page from the secure enclave is generated based on the determined state.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Rebekah M. Leslie-Hurd, Francis X. McKeen, Carlos V. Rozas, Gilbert Neiger, Asit K. Mallick, Ittai Anati, Ilya Alexandrovich, Vedvyas Shanbhogue, Somnath Chakrabarti
  • Patent number: 10289554
    Abstract: A processor implementing techniques to supporting fault information delivery is disclosed. In one embodiment, the processor includes a memory controller unit to access an enclave page cache (EPC) and a processor core coupled to the memory controller unit. The processor core to detect a fault associated with accessing the EPC and generate an error code associated with the fault. The error code reflects an EPC-related fault cause. The processor core is further to encode the error code into a data structure associated with the processor core. The data structure is for monitoring a hardware state related to the processor core.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: May 14, 2019
    Assignee: Intel Corporation
    Inventors: Rebekah M. Leslie-Hurd, Carlos V. Rozas, Francis X. Mckeen, Ilya Alexandrovich, Vedvyas Shanbhogue, Bin Xing, Mark W. Shanahan, Simon P. Johnson
  • Patent number: 10282306
    Abstract: A processor for supporting secure memory intent is disclosed. The processor of the disclosure includes a memory execution unit to access memory and a processor core coupled to the memory execution unit. The processor core is to receive a request to access a convertible page of the memory. In response to the request, the processor core to determine an intent for the convertible page in view of a page table entry (PTE) corresponding to the convertible page. The intent indicates whether the convertible page is to be accessed as at least one of a secure page or a non-secure page.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: May 7, 2019
    Assignee: Intel Corporation
    Inventors: Krystof C. Zmudzinski, Siddhartha Chhabra, Uday R. Savagaonkar, Simon P. Johnson, Rebekah M. Leslie-Hurd, Francis X. McKeen, Gilbert Neiger, Raghunandan Makaram, Carlos V. Rozas, Amy L. Santoni, Vincent R. Scarlata, Vedvyas Shanbhogue, Ilya Alexandrovich, Ittai Anati, Wesley H. Smith, Michael Goldsmith