Abstract: A processor to support platform migration of secure enclaves is disclosed. In one embodiment, the processor includes a memory controller unit to access secure enclaves and a processor core coupled to the memory controller unit. The processor core to identify a control structure associated with a secure enclave. The control structure comprises a plurality of data slots and keys associated with a first platform comprising the memory controller unit and the processor core. A version of data from the secure enclave is associated with the plurality of data slots. Migratable keys are generated as a replacement for the keys associated with the control structure. The migratable keys control access to the secure enclave. Thereafter, the control structure is migrated to a second platform to enable access to the secure enclave on the second platform.

Abstract: Embodiments of an invention for paging in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive a first instruction. The execution unit is to execute the first instruction, wherein execution of the first instruction includes evicting a first page from an enclave page cache.

Abstract: A system and related method for providing a highly reactive fuel to a combustor of a gas turbine are disclosed herein. The system includes a fuel supply system that is in fluid communication with a fuel supply. The fuel supply system includes multiple fuel circuits. Each fuel circuit individually feeds fuel to a corresponding fuel distribution manifold. The system further includes a steam injection system. The steam injection system includes at least one flow control valve that is in fluid communication with at least one of the fuel circuits. The flow control valve provides for fluid communication between a superheated steam source and the fuel circuit during both fueled operation and during non-fueled operation of the corresponding fuel circuit.

Abstract: A processor implementing techniques to supporting fault information delivery is disclosed. In one embodiment, the processor includes a memory controller unit to access an enclave page cache (EPC) and a processor core coupled to the memory controller unit. The processor core to detect a fault associated with accessing the EPC and generate an error code associated with the fault. The error code reflects an EPC-related fault cause. The processor core is further to encode the error code into a data structure associated with the processor core. The data structure is for monitoring a hardware state related to the processor core.

Abstract: A processor includes a decode unit to decode an instruction that is to indicate a page of a protected container memory, and a storage location outside of the protected container memory. An execution unit, in response to the instruction, is to ensure that there are no writable references to the page of the protected container memory while it has a write protected state. The execution unit is to encrypt a copy of the page of the protected container memory. The execution unit is to store the encrypted copy of the page to the storage location outside of the protected container memory, after it has been ensured that there are no writable references. The execution unit is to leave the page of the protected container memory in the write protected state, which is also valid and readable, after the encrypted copy has been stored to the storage location.

Abstract: Instructions and logic provide advanced paging capabilities for secure enclave page caches. Embodiments include multiple hardware threads or processing cores, a cache to store secure data for a shared page address allocated to a secure enclave accessible by the hardware threads. A decode stage decodes a first instruction specifying said shared page address as an operand, and execution units mark an entry corresponding to an enclave page cache mapping for the shared page address to block creation of a new translation for either of said first or second hardware threads to access the shared page. A second instruction is decoded for execution, the second instruction specifying said secure enclave as an operand, and execution units record hardware threads currently accessing secure data in the enclave page cache corresponding to the secure enclave, and decrement the recorded number of hardware threads when any of the hardware threads exits the secure enclave.

Abstract: Systems and methods provide a mechanism to create and maintain web pages and other types of output pages. The system and methods use an author markup language (AML) to define output pages. Additionally, a Component Markup Language (CML) may be used to define components that may be referenced by the AML. The AML and CML may be translated to an intermediate format, which may then be further processed at runtime to combine dynamic data with the intermediate format to produce the output page.

Abstract: A processor for supporting secure memory intent is disclosed. The processor of the disclosure includes a memory execution unit to access memory and a processor core coupled to the memory execution unit. The processor core is to receive a request to access a convertible page of the memory. In response to the request, the processor core to determine an intent for the convertible page in view of a page table entry (PTE) corresponding to the convertible page. The intent indicates whether the convertible page is to be accessed as at least one of a secure page or a non-secure page.

Abstract: Instructions and logic provide advanced paging capabilities for secure enclave page caches. Embodiments include multiple hardware threads or processing cores, a cache to store secure data for a shared page address allocated to a secure enclave accessible by the hardware threads. A decode stage decodes a first instruction specifying said shared page address as an operand, and execution units mark an entry corresponding to an enclave page cache mapping for the shared page address to block creation of a new translation for either of said first or second hardware threads to access the shared page. A second instruction is decoded for execution, the second instruction specifying said secure enclave as an operand, and execution units record hardware threads currently accessing secure data in the enclave page cache corresponding to the secure enclave, and decrement the recorded number of hardware threads when any of the hardware threads exits the secure enclave.

Abstract: An apparatus and method for securely suspending and resuming the state of a processor. For example, one embodiment of a method comprises: generating a data structure including at least the monotonic counter value; generating a message authentication code (MAC) over the data structure using a first key; securely providing the data structure and the MAC to a module executed on the processor; the module verifying the MAC, comparing the monotonic counter value with a counter value stored during a previous suspend operation and, if the counter values match, then loading processor state required for the resume operation to complete. Another embodiment of a method comprises: generating a first key by a processor; securely sharing the first key with an off-processor component; and using the first key to generate a pairing ID usable to identify a pairing between the processor and the off-processor component.

Abstract: Embodiments of the present disclosure describe devices, methods, computer-readable media and systems configurations for link adaptation within coordinated multipoint systems. In various embodiments, a mobile terminal may determine link adaptation feedback information and feed back the information to a base station. The base station may adjust a channel quality indicator of the link adaptation feedback information based on loading of nodes within a coordinated multipoint measurement set. Other embodiments may be described and/or claimed.

Abstract: An apparatus and method for securely suspending and resuming the state of a processor. For example, one embodiment of a method comprises: generating a data structure including at least the monotonic counter value; generating a message authentication code (MAC) over the data structure using a first key; securely providing the data structure and the MAC to a module executed on the processor; the module verifying the MAC, comparing the monotonic counter value with a counter value stored during a previous suspend operation and, if the counter values match, then loading processor state required for the resume operation to complete. Another embodiment of a method comprises: generating a first key by a processor; securely sharing the first key with an off-processor component; and using the first key to generate a pairing ID usable to identify a pairing between the processor and the off-processor component.

Abstract: Embodiments of an invention for memory management in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive a first instruction and a second instruction. The execution unit is to execute the first instruction, wherein execution of the first instruction includes allocating a page in an enclave page cache to a secure enclave. The execution unit is also to execute the second instruction, wherein execution of the second instruction includes confirming the allocation of the page.

Abstract: Embodiments of the present disclosure describe devices, methods, computer-readable media and systems configurations for transmission point indication in a coordinated multipoint (CoMP) system. A user equipment (UE) may receive common reference signal (CRS) parameters associated with individual base stations of a CoMP measurement set. The UE may also receive a transmission point index corresponding to a first base station of the CoMP measurement set that is scheduled for communications with the UE. A mapping module of the UE may produce a physical downlink shared channel (PDSCH) mapping pattern based on the CRS parameters associated with the scheduled base station.

Abstract: Systems and methods provide a mechanism to create and maintain web pages and other types of output pages. The system and methods use an author markup language (AML) to define output pages. Additionally, a Component Markup Language (CML) may be used to define components that may be referenced by the AML. The AML and CML may be translated to an intermediate format, which may then be further processed at runtime to combine dynamic data with the intermediate format to produce the output page.

Abstract: Embodiments of an invention for modifying memory permissions in a secure processing environment are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive an instruction to modify access permissions for a page in a secure enclave. The execution unit is to execute the instruction. Execution of the instruction includes setting new access permissions in an enclave page cache map entry. Furthermore, the page is immediately accessible from inside the secure enclave according to the new access permissions.

Abstract: Embodiments of the present disclosure describe techniques and configurations for handling signal quality measurements by a wireless device in a wireless network environment, particularly in a coordinated transmission environment. An apparatus may include computer-readable media having instructions and one or more processors coupled with the media and configured to execute the instructions to generate a power parameter corresponding to a power adjustment associated with a reference signal, provide the reference signal generated based in part on the generated power parameter to a wireless device, and provide the power parameter to transmission points operating in the coordinated transmission environment. Each of the transmission points may be configured to communicate the power parameter to the wireless device, and the wireless device may be configured to determine, based at least in part on the power parameter, a power characteristics associated with a channel in which the reference signal is provided.

Abstract: Embodiments of an invention for paging in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive a first instruction. The execution unit is to execute the first instruction, wherein execution of the first instruction includes evicting a first page from an enclave page cache.

Abstract: Embodiments of the present disclosure describe devices, methods, computer-readable media and systems configurations for transmission point indication in a coordinated multipoint (CoMP) system. A user equipment (UE) may receive common reference signal (CRS) parameters associated with individual base stations of a CoMP measurement set. The UE may also receive a transmission point index corresponding to a first base station of the CoMP measurement set that is scheduled for communications with the UE. A mapping module of the UE may produce a physical downlink shared channel (PDSCH) mapping pattern based on the CRS parameters associated with the scheduled base station.

Abstract: Embodiments of the present disclosure describe techniques and configurations for handling signal quality measurements by a wireless device in a wireless network environment, particularly in a coordinated transmission environment. An apparatus may include computer-readable media having instructions and one or more processors coupled with the media and configured to execute the instructions to generate a power parameter corresponding to a power adjustment associated with a reference signal, provide the reference signal generated based in part on the generated power parameter to a wireless device, and provide the power parameter to transmission points operating in the coordinated transmission environment. Each of the transmission points may be configured to communicate the power parameter to the wireless device, and the wireless device may be configured to determine, based at least in part on the power parameter, a power characteristics associated with a channel in which the reference signal is provided.