Abstract: A discontinuous or reduced thickness window layer can improve the efficiency of CdTe-based or other kinds of solar cells.

Abstract: A semiconductor memory device and a method for performing a memory operation in the semiconductor memory device are provided. The semiconductor memory device includes a plurality of predetermined memory arrays, a bitline decoder, and a controller. The controller provides the memory operation signal to the bitline decoder and, after precharging bitlines of the plurality of predetermined memory arrays, performs the memory operation on selected memory cells in the one or more of the plurality of predetermined memory arrays in accordance with the memory operation signal. The bitline decoder includes a plurality of sector select transistors and determines selected ones of the plurality of predetermined memory arrays and selected rows and unselected rows within the selected ones of the plurality of predetermined memory arrays in response to the memory operation signal.

Abstract: A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer.

Abstract: A bearing component 2 for a joint replacement prosthesis comprises a first bearing element 4; a second bearing element 6, and a linking element 8, operatively connecting the first and second bearing elements 4, 6 and permitting relative motion there between. The flexible linking element 8 prevents dislocation of mobile bearings in a total knee replacement prosthesis. The invention also relates to a bridging element which retains the linking element 8 with some play, which acts as a ligament support 2051, and which causes a deflection of the line of action of a ligament 1018. A joint replacement prosthesis is also disclosed comprising a biasing element 1140 or a tensioning element 1220 operatively coupled to the artificial ligament 1018. The biasing element 1140 or tensioning element 1220 may be housed in the stem of a tibial tray 1006.

Abstract: Making gates having multiple thicknesses on the same substrate in a given process flow is provided. For example, a method of making a semiconductor structure having at least two gates of different thickness involves forming a first gate layer having a first thickness; patterning a first hard mask over a portion of the first gate layer to define a first gate underneath the first hard mask having a first gate thickness; forming a second gate layer having a second thickness over the first gate layer and the first hard mask; patterning a second hard mask over a portion of the second gate layer to define a second gate underneath the second hard mask having a second gate thickness; removing portions of the first gate layer and the second gate layer that are not under the first hard mask and the second hard mask; and removing the first hard mask and the second hard mask to provide two gates of different thicknesses.

Abstract: A low noise (1/f) junction field effect transistor (JFET) is disclosed, wherein multiple implants push a conduction path of the transistor away from the surface of a layer upon which the transistor is formed. In this manner, current flow in the conduction path is less likely to be disturbed by defects that may exist at the surface of the layer, thereby mitigating (1/f) noise.

Abstract: Fashioning a low noise (1/f) junction field effect transistor (JFET) is disclosed, where multiple implants are performed to push a conduction path of the transistor away from the surface of a layer upon which the transistor is formed. In this manner, current flow in the conduction path is less likely to be disturbed by defects that may exist at the surface of the layer, thereby mitigating (1/f) noise.

Abstract: Making gates having multiple thicknesses on the same substrate in a given process flow is provided. For example, a method of making a semiconductor structure having at least two gates of different thickness involves forming a first gate layer having a first thickness; patterning a first hard mask over a portion of the first gate layer to define a first gate underneath the first hard mask having a first gate thickness; forming a second gate layer having a second thickness over the first gate layer and the first hard mask; patterning a second hard mask over a portion of the second gate layer to define a second gate underneath the second hard mask having a second gate thickness; removing portions of the first gate layer and the second gate layer that are not under the first hard mask and the second hard mask; and removing the first hard mask and the second hard mask to provide two gates of different thicknesses.

Abstract: Fashioning a low noise (1/f) junction field effect transistor (JFET) is disclosed, where multiple implants are performed to push a conduction path of the transistor away from the surface of a layer upon which the transistor is formed. In this manner, current flow in the conduction path is less likely to be disturbed by defects that may exist at the surface of the layer, thereby mitigating (1/f) noise.

Abstract: A web-browser plug-in is described herein that detects the type of content a user selects on a web page and allows the user to retrieve additional information about selected web content or initiate a communication application. The plug-in analyzes the user's selection to determine what type of web content was selected. A smart menu is created and presented to the user with options relating to the type of web content selected. The user can then either download additional information about the web content or initiate a communication application without having to navigate to another web page or request information from a web service. Without having to navigate to a second web page, the user can select an option and either view the additional web information or initiate the communication application.

Abstract: The invention provides, in one aspect, a method of fabricating a semiconductor device. This embodiment comprises depositing a gate layer over a gate dielectric layer located over a semiconductor substrate, and incorporating fluorine into the gate dielectric layer before doping the gate layer.

Abstract: Junction field effect transistors (JFETs) can be fabricated with an epitaxial layer that forms a sufficiently thick channel region to enable the JFET for use in high voltage applications (e.g., having a breakdown voltage greater than about 20V). Additionally or alternatively, threshold voltage (VT) implants can be introduced at one or more of the gate, source and drain regions to improve noise performance of the JFET. Additionally, fabrication of such a JFET can be facilitated forming the entire JFET structure concurrently with a CMOS fabrication process and/or with a BiCMOS fabrication process.

Abstract: A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer.

Abstract: A method of fabricating a semiconductor device having a triple LDD (lateral diffused dopants) structure is disclosed. This fabrication method requires a single implant process, leading to reduction in fabrication costs and fabrication time. Moreover, this fabrication method increases the surface area of the gate structure of the semiconductor device that is available for silicide to be formed, leading to lower gate resistance.

Abstract: A method for manufacturing a memory device includes forming an oxide layer adjacent a substrate. A floating gate layer is formed and disposed outwardly from the oxide layer. A dielectric layer is formed, such that it is disposed outwardly from the floating gate layer. Then, a conductive material layer is formed and disposed outwardly from the dielectric layer, wherein the conductive material layer forms a control gate that is substantially isolated from the floating gate layer by the dielectric layer.

Abstract: A method for manufacturing a semiconductor device that comprises forming an oxide layer over a substrate. A polysilicon layer is disposed outwardly from the oxide layer, wherein the polysilicon layer forms a floating gate. A PSG layer is disposed outwardly from the polysilicon layer and planarized. The device is pattern etched to form a capacitor channel, wherein the capacitor channel is disposed substantially above the floating gate formed from the polysilicon layer. A dielectric layer is formed in the capacitor channel disposed outwardly from the polysilicon layer. A tungsten plug operable to substantially fill the capacitor channel is formed.

Abstract: A method of fabricating a semiconductor device having a triple LDD (lateral diffused dopants) structure is disclosed. This fabrication method requires a single implant process, leading to reduction in fabrication costs and fabrication time. Moreover, this fabrication method increases the surface area of the gate structure of the semiconductor device that is available for silicide to be formed, leading to lower gate resistance.

Abstract: A method for reducing the drain resistance of a drain-extended MOS transistor in a semiconductor wafer, while maintaining a high transistor breakdown voltage. The method provides a first well (502) of a first conductivity type, operable as the extension of the transistor drain (501) of the first conductivity type; portions of the well are covered by a first insulator (503) having a first thickness. A second well (504) of the opposite conductivity type is intended to contain the transistor source (506) of the first conductivity type; portions of the second well are covered by a second insulator (507) thinner than the first insulator. The first and second wells form a junction (505) that terminates at the second insulator (530a, 530b). The method deposits a photoresist layer (510) over the wafer, which is patterned by opening a window (510a) that extends from the drain to the junction termination.

Abstract: Junction field effect transistors (JFETs) can be fabricated with an epitaxial layer that forms a sufficiently thick channel region to enable the JFET for use in high voltage applications (e.g., having a breakdown voltage greater than about 20V). Additionally or alternatively, threshold voltage (VT) implants can be introduced at one or more of the gate, source and drain regions to improve noise performance of the JFET. Additionally, fabrication of such a JFET can be facilitated forming the entire JFET structure concurrently with a CMOS fabrication process and/or with a BiCMOS fabrication process.

Abstract: A method for reducing the drain resistance of a drain-extended MOS transistor in a semiconductor wafer, while maintaining a high transistor breakdown voltage. The method provides a first well (502) of a first conductivity type, operable as the extension of the transistor drain (501) of the first conductivity type; portions of the well are covered by a first insulator (503) having a first thickness. A second well (504) of the opposite conductivity type is intended to contain the transistor source (506) of the first conductivity type; portions of the second well are covered by a second insulator (507) thinner than the first insulator. The first and second wells form a junction (505) that terminates at the second insulator (530a, 530b). The method deposits a photoresist layer (510) over the wafer, which is patterned by opening a window (510a) that extends from the drain to the junction termination.