Patents by Inventor Imran Khan

Imran Khan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8110857
    Abstract: A low noise (1/f) junction field effect transistor (JFET) is disclosed, wherein multiple implants push a conduction path of the transistor away from the surface of a layer upon which the transistor is formed. In this manner, current flow in the conduction path is less likely to be disturbed by defects that may exist at the surface of the layer, thereby mitigating (1/f) noise.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: February 7, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Pinghai Hao, Imran Khan, Joe Trogolo
  • Publication number: 20110270404
    Abstract: A prosthetic bearing component (10) comprising a bearing surface (40), wherein in use one or more openings (20) are provided on the bearing surface (40) and wherein the one or more openings (20) are suitable for receiving one or more attachment means (30) to secure the prosthetic bearing component (10) in place.
    Type: Application
    Filed: August 27, 2009
    Publication date: November 3, 2011
    Applicant: BIOMET UK LIMITED
    Inventors: Mohammed Imran Khan, Robert John Andrew Bigsby, Robert Andrew Scott, David Wayne Schroeder
  • Patent number: 8040738
    Abstract: A semiconductor memory device and a method for performing a memory operation in the semiconductor memory device are provided. The semiconductor memory device includes a plurality of predetermined memory arrays, a bitline decoder, and a controller. The controller provides the memory operation signal to the bitline decoder and, after precharging bitlines of the plurality of predetermined memory arrays, performs the memory operation on selected memory cells in the one or more of the plurality of predetermined memory arrays in accordance with the memory operation signal. The bitline decoder includes a plurality of sector select transistors and determines selected ones of the plurality of predetermined memory arrays and selected rows and unselected rows within the selected ones of the plurality of predetermined memory arrays in response to the memory operation signal.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: October 18, 2011
    Assignee: Spansion LLC
    Inventors: Hagop Nazarian, Imran Khan, Chieu-Yin Chia
  • Publication number: 20110237021
    Abstract: A method for manufacturing a photovoltaic module including a laminating step.
    Type: Application
    Filed: February 25, 2011
    Publication date: September 29, 2011
    Applicant: First Solar, Inc.
    Inventors: Markus Gloeckler, Imran Khan
  • Publication number: 20110176363
    Abstract: A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer.
    Type: Application
    Filed: March 29, 2011
    Publication date: July 21, 2011
    Applicant: SPANSION LLC
    Inventors: Shibly S. AHMED, Jun KANG, Hsiao-Han THIO, Imran KHAN, Dong-Hyuk JU, Chuan LIN
  • Publication number: 20110139240
    Abstract: A discontinuous or reduced thickness window layer can improve the efficiency of CdTe-based or other kinds of solar cells.
    Type: Application
    Filed: December 15, 2010
    Publication date: June 16, 2011
    Applicant: First Solar, Inc.
    Inventors: Arnold Allenic, Benyamin Buller, Markus Gloeckler, Imran Khan, Viral Parikh, Rick C. Powell, Igor Sankin, Gang Xiong
  • Publication number: 20110122708
    Abstract: A semiconductor memory device and a method for performing a memory operation in the semiconductor memory device are provided. The semiconductor memory device includes a plurality of predetermined memory arrays, a bitline decoder, and a controller. The controller provides the memory operation signal to the bitline decoder and, after precharging bitlines of the plurality of predetermined memory arrays, performs the memory operation on selected memory cells in the one or more of the plurality of predetermined memory arrays in accordance with the memory operation signal. The bitline decoder includes a plurality of sector select transistors and determines selected ones of the plurality of predetermined memory arrays and selected rows and unselected rows within the selected ones of the plurality of predetermined memory arrays in response to the memory operation signal.
    Type: Application
    Filed: December 30, 2008
    Publication date: May 26, 2011
    Applicant: SPANSION LLC
    Inventors: Hagop NAZARIAN, Imran KHAN, Chieu-Yin CHIA
  • Patent number: 7939440
    Abstract: A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: May 10, 2011
    Assignee: Spansion LLC
    Inventors: Shibly S. Ahmed, Jun Kang, Hsiao-Han Thio, Imran Khan, Dong-Hyuk Ju, Chuan Lin
  • Publication number: 20110106265
    Abstract: A bearing component 2 for a joint replacement prosthesis comprises a first bearing element 4; a second bearing element 6, and a linking element 8, operatively connecting the first and second bearing elements 4, 6 and permitting relative motion there between. The flexible linking element 8 prevents dislocation of mobile bearings in a total knee replacement prosthesis. The invention also relates to a bridging element which retains the linking element 8 with some play, which acts as a ligament support 2051, and which causes a deflection of the line of action of a ligament 1018. A joint replacement prosthesis is also disclosed comprising a biasing element 1140 or a tensioning element 1220 operatively coupled to the artificial ligament 1018. The biasing element 1140 or tensioning element 1220 may be housed in the stem of a tibial tray 1006.
    Type: Application
    Filed: October 31, 2008
    Publication date: May 5, 2011
    Applicant: BIOMET UK LIMITED
    Inventors: David Wolfson, Russell Lloyd, John O'connor, Mohammed Imran Khan, David Wycliffe Murray, Christopher Dodo, John W. Goodfellow
  • Patent number: 7776696
    Abstract: Making gates having multiple thicknesses on the same substrate in a given process flow is provided. For example, a method of making a semiconductor structure having at least two gates of different thickness involves forming a first gate layer having a first thickness; patterning a first hard mask over a portion of the first gate layer to define a first gate underneath the first hard mask having a first gate thickness; forming a second gate layer having a second thickness over the first gate layer and the first hard mask; patterning a second hard mask over a portion of the second gate layer to define a second gate underneath the second hard mask having a second gate thickness; removing portions of the first gate layer and the second gate layer that are not under the first hard mask and the second hard mask; and removing the first hard mask and the second hard mask to provide two gates of different thicknesses.
    Type: Grant
    Filed: April 30, 2007
    Date of Patent: August 17, 2010
    Assignee: Spansion LLC
    Inventors: Imran Khan, Ahmed Shibly, Dong-Hyuk Ju
  • Publication number: 20100155789
    Abstract: A low noise (1/f) junction field effect transistor (JFET) is disclosed, wherein multiple implants push a conduction path of the transistor away from the surface of a layer upon which the transistor is formed. In this manner, current flow in the conduction path is less likely to be disturbed by defects that may exist at the surface of the layer, thereby mitigating (1/f) noise.
    Type: Application
    Filed: February 26, 2010
    Publication date: June 24, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Pinghai Hao, Imran Khan, Joe Trogolo
  • Patent number: 7670888
    Abstract: Fashioning a low noise (1/f) junction field effect transistor (JFET) is disclosed, where multiple implants are performed to push a conduction path of the transistor away from the surface of a layer upon which the transistor is formed. In this manner, current flow in the conduction path is less likely to be disturbed by defects that may exist at the surface of the layer, thereby mitigating (1/f) noise.
    Type: Grant
    Filed: April 11, 2007
    Date of Patent: March 2, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Pinghai Hao, Imran Khan, Joe Trogolo
  • Publication number: 20080268630
    Abstract: Making gates having multiple thicknesses on the same substrate in a given process flow is provided. For example, a method of making a semiconductor structure having at least two gates of different thickness involves forming a first gate layer having a first thickness; patterning a first hard mask over a portion of the first gate layer to define a first gate underneath the first hard mask having a first gate thickness; forming a second gate layer having a second thickness over the first gate layer and the first hard mask; patterning a second hard mask over a portion of the second gate layer to define a second gate underneath the second hard mask having a second gate thickness; removing portions of the first gate layer and the second gate layer that are not under the first hard mask and the second hard mask; and removing the first hard mask and the second hard mask to provide two gates of different thicknesses.
    Type: Application
    Filed: April 30, 2007
    Publication date: October 30, 2008
    Applicant: SPANSION LLC
    Inventors: Imran Khan, Ahmed Shibly, Dong-Hyuk Ju
  • Publication number: 20080251818
    Abstract: Fashioning a low noise (1/f) junction field effect transistor (JFET) is disclosed, where multiple implants are performed to push a conduction path of the transistor away from the surface of a layer upon which the transistor is formed. In this manner, current flow in the conduction path is less likely to be disturbed by defects that may exist at the surface of the layer, thereby mitigating (1/f) noise.
    Type: Application
    Filed: April 11, 2007
    Publication date: October 16, 2008
    Inventors: Pinghai Hao, Imran Khan, Joe Trogolo
  • Publication number: 20080195954
    Abstract: A web-browser plug-in is described herein that detects the type of content a user selects on a web page and allows the user to retrieve additional information about selected web content or initiate a communication application. The plug-in analyzes the user's selection to determine what type of web content was selected. A smart menu is created and presented to the user with options relating to the type of web content selected. The user can then either download additional information about the web content or initiate a communication application without having to navigate to another web page or request information from a web service. Without having to navigate to a second web page, the user can select an option and either view the additional web information or initiate the communication application.
    Type: Application
    Filed: February 9, 2007
    Publication date: August 14, 2008
    Applicant: Microsoft Corporation
    Inventors: Baskaran Dharmarajan, Dennis Takchi Cheung, Eliot Spencer Savarese, Mukund Narasimhan, Imran Khan, Denise K. Ho
  • Publication number: 20070218663
    Abstract: The invention provides, in one aspect, a method of fabricating a semiconductor device. This embodiment comprises depositing a gate layer over a gate dielectric layer located over a semiconductor substrate, and incorporating fluorine into the gate dielectric layer before doping the gate layer.
    Type: Application
    Filed: March 20, 2006
    Publication date: September 20, 2007
    Applicant: Texas Instruments Inc.
    Inventors: Pinghai Hao, Imran Khan, Fan-Chi Hou
  • Patent number: 7268394
    Abstract: Junction field effect transistors (JFETs) can be fabricated with an epitaxial layer that forms a sufficiently thick channel region to enable the JFET for use in high voltage applications (e.g., having a breakdown voltage greater than about 20V). Additionally or alternatively, threshold voltage (VT) implants can be introduced at one or more of the gate, source and drain regions to improve noise performance of the JFET. Additionally, fabrication of such a JFET can be facilitated forming the entire JFET structure concurrently with a CMOS fabrication process and/or with a BiCMOS fabrication process.
    Type: Grant
    Filed: January 18, 2005
    Date of Patent: September 11, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Pinghai Hao, Fan-Chi Hou, Imran Khan
  • Publication number: 20070052002
    Abstract: A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer.
    Type: Application
    Filed: June 15, 2005
    Publication date: March 8, 2007
    Inventors: Shibly Ahmed, Jun Kang, Hsiao-Han Thio, Imran Khan, Dong-Hyuk Ju, Chuan Lin
  • Patent number: 7084458
    Abstract: A method of fabricating a semiconductor device having a triple LDD (lateral diffused dopants) structure is disclosed. This fabrication method requires a single implant process, leading to reduction in fabrication costs and fabrication time. Moreover, this fabrication method increases the surface area of the gate structure of the semiconductor device that is available for silicide to be formed, leading to lower gate resistance.
    Type: Grant
    Filed: May 2, 2005
    Date of Patent: August 1, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Imran Khan, Jianshi Wang, Yue-Song He, Jun Kang
  • Patent number: 6958269
    Abstract: A method for manufacturing a memory device includes forming an oxide layer adjacent a substrate. A floating gate layer is formed and disposed outwardly from the oxide layer. A dielectric layer is formed, such that it is disposed outwardly from the floating gate layer. Then, a conductive material layer is formed and disposed outwardly from the dielectric layer, wherein the conductive material layer forms a control gate that is substantially isolated from the floating gate layer by the dielectric layer.
    Type: Grant
    Filed: June 24, 2002
    Date of Patent: October 25, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Josef Czeslaw Mitros, Imran Khan, Lily Springer