Abstract: A polymer plastic front plate comprises: a plastic substrate and a hard coating layer formed on an adhesion surface of the plastic substrate. The hard coating layer comprises: organic-inorganic hybrid UV oligomer, high Tg UV resin additive, a plurality of dispersed flaky nano inorganic material, and photo initiator, so as to form a gas barrier hard coating layer with high surface dyne value (>44 dyne) on the adhesion surface of the plastic substrate. It not only has good ink printability and OCA adhesiveness, but also inhibits the diffusion of fugitive gas from polymer plastic front plates during high-temperature, high-temperature and high-humidity, high-low temperature thermal shocks and other harsh automotive industry environmental tests. The gas can be avoided from entering the OCA layer, thereby solving the problems of bubbles and delamination after the environmental tests are performed.

Abstract: A connecting device including a housing, a connector and an elastic element is provided. The housing comprises a connector base including a bottom plate and a side wall, the bottom plate and the side wall jointly surround a space. The connector is disposed at the connector base and located in the space. The connector includes a positioning element and a plug terminal element connected to the positioning element. The positioning element including a limit portion is connected with the plug terminal element. The elastic element abuts between the plug terminal element and the bottom plate. When the plug terminal element is moved to a skewed position by an external force, the limit portion is moved away from the bottom plate. When the external force is disappeared, the limit portion returns to abut against the bottom plate, such that the plug element is in an upright position.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a gate structure formed over a substrate, and a first source/drain (S/D) structure formed adjacent to the gate structure. The semiconductor structure includes an S/D contact structure formed over the first S/D structure, and a dielectric wall formed below the gate structure and the S/D contact structure. The dielectric wall has a first portion directly below the S/D contact structure and a second portion directly below the gate structure, the first portion has a first height along a vertical direction, the second portion has a second height along the vertical direction, and the first height is smaller than the second height.

Abstract: A first integrated circuit (IC) die includes a first substrate. A second IC die includes a second substrate. At least one of the first substrate or the second substrate has a first surface orientation. The first IC die is spaced apart from the second IC die. A third die electrically interconnects the first IC die to the second IC die. The third die includes a third substrate having a second surface orientation. The second surface orientation is different from the first surface orientation.

Abstract: A programming method of a non-volatile memory cell is provided. The non-volatile memory cell includes a memory transistor. Firstly, a current limiter is provided, and the current limiter is connected between a drain terminal of the memory transistor and a ground terminal. Then, a program voltage is provided to a source terminal of the memory transistor, and a control signal is provided to a gate terminal of the memory transistor. In a first time period of a program action, the control signal is gradually decreased from a first voltage value, so that the memory transistor is firstly turned off and then slightly turned on. When the memory transistor is turned on, plural hot electrons are injected into a charge trapping layer of the memory transistor.

Abstract: This patent application discloses an innovative attachment system designed to connect resistance bands to exercise apparatuses. Comprising two main components, including an anchor with diverse designs, a flange, and a threaded bolt, the attachment system offers versatile options for exercise enthusiasts. Additionally, a complementary part featuring a wing nut and a matching flange ensures secure attachment to exercise equipment like power racks with varying hole sizes. Crafted from durable materials like steel, stainless steel, aluminum, copper, titanium, or their alloys, this attachment system combines durability with ease of use, facilitating resistance-band workouts, dynamic bodyweight training systems, and more. Its versatility, portability, and simplicity of design make it a valuable addition to the fitness equipment landscape.

Abstract: A semiconductor device and a method are provided. The semiconductor device includes a first semiconductor component, a bonding layer and a second semiconductor component. The first semiconductor component includes a first transistor formed on a substrate and a second transistor formed on the substrate and separated from the first transistor. The bonding layer is provided on the first semiconductor component. The second semiconductor component is provided on the bonding layer and includes an acoustic transducer. The acoustic transducer is controlled by the first transistor and the second transistor to execute a photoacoustic sensing. The acoustic transducer comprises a space gap and a least a portion of the space gap is surrounded by the bonding layer.

Abstract: An image sensing device includes a frame body, a lens group, a position adjuster, multiple antenna elements, and an image sensing element. The frame body has an accommodating space. The lens group is disposed in the accommodating space. The position adjuster is connected between the lens group and the frame body, and configured to allow the lens group to move in the accommodating space. The antenna elements are disposed on a second side of the lens group, and configured to provide sensing beams to a target area. The image sensing element is disposed on the second side of the lens group, and configured to sense reflected light beams of the target area. In addition, a head-mounted display device is also provided.

Abstract: The disclosure provides a method for forming an electrostatic discharge (ESD) protection circuit. The method includes providing a circuit comprising a first voltage supply line, an internal circuit, an input/output (I/O) pad coupling to the internal circuit through a line, and a first ESD protection element between the I/O pad and the internal circuit, wherein the first ESD protection element includes a plurality of first ESD units; and forming a first connection circuit on the first ESD protection element, to couple a first group of the first ESD units to the first voltage supply line though a first node and couple the first group of the first ESD units to the line though a second node.

Abstract: A semiconductor image sensing structure includes a substrate, an isolation structure, an anti-reflection structure, at least one optical element and a transistor. The substrate has at least one photodiode region. The isolation structure is disposed in the substrate and surrounds the photodiode region. The anti-reflection structure covers the photodiode region. The optical element is disposed over the anti-reflection structure and corresponds to the photodiode region. The transistor is disposed under the photodiode region.

Abstract: A flexible shoulder pin module includes a barrel having an annular head portion, a cylindrical body portion, and a through-hole extending from a top surface of the body portion to a bottom end of the head portion; and a shoulder pin having a shaft portion and a shoulder portion formed thereon. The through-hole includes a first portion adjacent to the top surface of the body portion, and a second portion having a greater diameter than the first portion. The shaft portion is insertable through the first portion into the second portion. The shoulder portion is configured to adjustably extend above the top surface of the body portion to clamp a panel thereto. A compressible device is configured to be disposed around the shaft portion and secured by a stopper panel, which is coupled to the shaft portion and placed adjacent to the head portion within the second portion.

Abstract: The present disclosure provides a semiconductor structure including a base layer, a first conductive line disposed on the base layer, a first dielectric pillar disposed on the base layer, a second dielectric pillar disposed on the base layer, a first liner, and a second liner. The first conductive line is disposed between the first dielectric pillar and the second dielectric pillar. The first liner encloses a first air gap, and is disposed between the first dielectric pillar and the first conductive line. The second liner encloses a second air gap, and is disposed between the second dielectric pillar and the first conductive line.

Abstract: Various embodiments relate to event processing. A system may include a mobile unit, which may include one or more sensors configured for capturing data and a controller for generating a number of events based on captured data. The system may further include a complex event processing (CEP) system communicatively coupled to the mobile unit. The CEP system may be configured to receive one or more of the number of events and generate one or more actions based on the one or more number of events. Associated systems, methods, and computer-readable media are also disclosed.

Abstract: An RRAM includes a bottom electrode, a resistive switching layer and a top electrode. The bottom electrode includes an inverted T-shaped profile. The resistive switching layer covers the bottom electrode. The top electrode covers the resistive switching layer. The inverted T-shaped profile includes a bottom element and a vertical element. The vertical element is disposed on the bottom element. The shape of the vertical element includes a rectangle or a trapezoid.

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a semiconductor layer, a micro-electromechanical systems (MEMS) structure defined in the semiconductor layer, a bond ring over the semiconductor layer, and a cap structure over the MEMS structure and bonded to the bond ring. The MEMS structure has an upper surface and the cap structure has a lower surface facing the upper surface of the MEMS structure. Dimples of eutectic material are on the upper surface of the MEMS structure.

Abstract: Methods and systems for anonymizing an identity of a caller using a voice print match. One system includes a surveillance system including a camera and a microphone; and a dispatch computer. The dispatch computer is configured to receive a voice call from the caller, generate a voice print from the voice call, compare the voice print to a plurality of stored voice prints, and, in response to the voice print not matching any of the plurality of stored voice prints, transmit the voice print to the surveillance system. The surveillance system is configured to receive the voice print, capture audio data via the microphone, compare the audio data to the voice print, and, in response to identifying a match between the voice print and the audio data, tag image data, captured via the camera, corresponding to the audio data for redaction.

Abstract: The disclosure relates to methods of analyzing a post-translationally modified protein of interest using electrophoresis, the methods comprising deglycosylating the protein of interest after labeling.

Abstract: A forming machine for a pulp product includes a frame unit defining a forming zone, two hot pressing zones, and two demolding zones; a forming unit disposed in the forming zone and including a forming mold for scooping pulp from a pulp tank and forming a blank unit thereon for every scoop of the pulp; a lower mold unit including four lower molds movable relative to the frame unit along a vertical direction, and an upper mold unit movable between two positions along a moving direction in a repetitive manner and including two upper hot-pressing central molds and two upper hot-pressing transfer molds. The upper mold unit is engageable with the forming mold and a corresponding one of the lower molds in different positions.

Abstract: An electronic device includes a communicator; at least one memory storing information associated with a neural network model for predicting a target device for each time zone from a plurality of time zones for an advertising content; and at least one processor configured to: acquire, from a plurality of external devices, data corresponding to a use history of a user; acquire, based on the data corresponding to the use history, a plurality of feature values corresponding to a respective external device from the plurality of external devices by allocation of each feature value of the plurality of feature values to a respective time zone from the plurality of time zones, input the plurality of feature values into the neural network model, and acquire score information for a plurality of probabilities that the plurality of external devices are related to a label by allocation of each probability of the plurality of probabilities to a respective time zone from the plurality of time zones, identify, based on the sc

Abstract: A level shifter includes a cross-coupled transistor pair, first through third cascode transistor pairs and a differential input pair sequentially coupled in series, and further includes a sub level shifter. The first cascode transistor pair is controlled by a first reference voltage. The second cascode transistor pair is controlled by a pair of differential control voltages. The third cascode transistor pair is controlled by a second reference voltage lower than the first reference voltage. The differential input pair is controlled by a pair of differential input voltages. The sub level shifter generates the differential control voltages according to the differential input voltages and the first and second reference voltages. The differential control voltages are switched between the first and second reference voltages. The level shifter outputs a pair of differential output voltages through inverted and non-inverted output terminals coupled with the second cascode transistor pair.