Patents by Inventor In Gon YANG

In Gon YANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11882703
    Abstract: Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device may include a stacked body including a plurality of interlayer insulating layers and a plurality of gate electrodes that are alternately stacked on a substrate, and a plurality of channel structures configured to vertically pass through the stacked body. Each of the plurality of channel structures may include a core insulating layer, a first channel layer, a second channel layer, a tunnel insulating layer, and a charge storage layer that extend vertically towards the substrate. Electron mobility of the first channel layer may be higher than electron mobility of the second channel layer.
    Type: Grant
    Filed: July 15, 2021
    Date of Patent: January 23, 2024
    Assignee: SK hynix Inc.
    Inventors: Sungmook Lim, Dae Hwan Yun, Gil Bok Choi, Jae Hyeon Shin, In Gon Yang, Hyung Jin Choi
  • Publication number: 20230420696
    Abstract: The present disclosure relates to a method for manufacturing core-shell particles using carbon monoxide, and more particularly, to a method for manufacturing core-shell particles, the method of which a simple and fast one-pot reaction enables particle manufacturing to reduce process costs, facilitate scale-up, change various types of core and shell metals, and form a multi-layered shell by including the steps of adsorbing carbon monoxide on a transition metal for a core, and reacting carbon monoxide adsorbed on the surface of the transition metal for the core, a metal precursor for a shell, and a solvent to form particles with a core-shell structure having a reduced metal shell layer formed on a transition metal core.
    Type: Application
    Filed: September 12, 2023
    Publication date: December 28, 2023
    Applicant: KOREA INSTITUTE OF ENERGY RESEARCH
    Inventors: Gu-gon PARK, Eun Jik LEE, Kyunghee KIM, Sung-dae YIM, Seok-hee PARK, Min-ji KIM, Young-jun SOHN, Byungchan BAE, Seung-gon KIM, Dongwon SHIN, Hwanyeong OH, Seung Hee WOO, So Jeong LEE, Hyejin LEE, Yoon Young CHOI, Won-yong LEE, Tae-hyun YANG
  • Publication number: 20230402619
    Abstract: A method for preparing a platinum alloy catalyst using an oxide coating according to an embodiment of the present disclosure comprises: a first step of preparing a dispersion by mixing a commercial platinum catalyst and a transition metal precursor with a solvent; a second step of preparing a catalyst by putting an ultrasonic tip into the dispersion prepared through the first step and performing an ultrasonic process; a third step of performing a primary heat treatment process on the catalyst prepared through the second step; a fourth step of performing an acid treatment process on the catalyst that has undergone the primary heat treatment process through the third step; and a fifth step of preparing a platinum alloy catalyst by performing a secondary heat treatment process on the catalyst that has undergone the acid treatment process through the fourth step.
    Type: Application
    Filed: March 23, 2023
    Publication date: December 14, 2023
    Applicant: KOREA INSTITUTE OF ENERGY RESEARCH
    Inventors: Eun Jik LEE, Gu-gon PARK, DongJe LEE, Sung-dae YIM, Seok-hee PARK, Min-jin KIM, Young-jun SOHN, Byungchan BAE, Seung-gon KIM, Dongwon SHIN, Hwanyeong OH, Seung Hee WOO, So Jeong LEE, Hyejin LEE, Yoon Young CHOI, Yun Sik KANG, Won-yong LEE, Tae-hyun YANG
  • Publication number: 20230378480
    Abstract: The manufacturing method of a palladium transition metal core-based core-shell electrode catalyst according to an exemplary embodiment of the present disclosure includes a first step of preparing a slurry by irradiating ultrasonic wave to a dispersion solution including a solvent, a platinum precursor, a palladium precursor, a carbon support, and a transition metal precursor, a second step of preparing a solid material by filtering, washing, and drying the slurry prepared in the first step, and a third step of preparing a core-shell electrode catalyst by thermally treating the solid prepared in the second step in a specific gas atmosphere.
    Type: Application
    Filed: January 31, 2023
    Publication date: November 23, 2023
    Applicant: KOREA INSTITUTE OF ENERGY RESEARCH
    Inventors: Gu-gon PARK, Eunjik LEE, Ik Sung LIM, Sung-Dae YIM, Seok-Hee PARK, Minjin KIM, Young-Jun SOHN, Byungchan BAE, Seung-gon KIM, Dongwon SHIN, Hwanyeong OH, Seung Hee WOO, So Jeong LEE, Hyejin LEE, Yoon Young CHOI, Yun Sik KANG, Won-yong LEE, Tae-hyun YANG
  • Patent number: 11813600
    Abstract: The present disclosure is related to a method for preparing a gaseous- or liquid-nitridation treated core-shell catalyst and, more specifically, to a method for preparing a gaseous- or liquid-nitridation treated core-shell catalyst comprising steps of: nitridation-treating a transition metal precursor core and noble metal precursor shell particles in the presence of a gaseous nitrogen source; or forming a transition metal precursor core and noble metal precursor shell particles, by means of a liquid nitrogen source, and at the same time allowing the nitrogen source to bond with the transition metal precursor and thus allowing nitridation treatment. Therefore, the present disclosure allows a high nitrogen content in the core and thus enables a prepared catalyst to have excellent durability, a small average particle size and high degree of dispersion and uniformity, and thus to be suitable for the fuel cell field.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: November 14, 2023
    Assignee: KOREA INSTITUTE OF ENERGY RESEARCH
    Inventors: Gu-gon Park, Eun-jik Lee, Dong-chul Park, Sung-dae Yim, Chang-soo Kim, Won-yong Lee, Tae-hyun Yang, Seok-hee Park, Min-jin Kim, Young-jun Sohn, Byung-chan Bae, Seung-gon Kim, Dong-won Shin, Hwan-yeong Oh
  • Patent number: 11791475
    Abstract: The present disclosure relates to a method for manufacturing core-shell particles using carbon monoxide, and more particularly, to a method for manufacturing core-shell particles, the method of which a simple and fast one-pot reaction enables particle manufacturing to reduce process costs, facilitate scale-up, change various types of core and shell metals, and form a multi-layered shell by including the steps of adsorbing carbon monoxide on a transition metal for a core, and reacting carbon monoxide adsorbed on the surface of the transition metal for the core, a metal precursor for a shell, and a solvent to form particles with a core-shell structure having a reduced metal shell layer formed on a transition metal core.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: October 17, 2023
    Assignee: Korea Institute of Energy Research
    Inventors: Gu-Gon Park, Eun Jik Lee, Kyunghee Kim, Sung-dae Yim, Seok-hee Park, Min-ji Kim, Young-jun Sohn, Byungchan Bae, Seung-gon Kim, Dongwon Shin, Hwanyeong Oh, Seung Hee Woo, So Jeong Lee, Hyejin Lee, Yoon Young Choi, Won-Yong Lee, Tae-hyun Yang
  • Patent number: 11781211
    Abstract: In a method for coating on a surface of a medical PEEK material with titanium to have a microporous structure, titanium is coated on a surface of polyether ether ketone (PEEK) via magnetron sputtering. The surface of the titanium coated on the surface of PEEK is polished via an electromagnetic polishing apparatus. A thin-film with titanium dioxide (TiO2) having a microporous structure is formed on the polished surface of the titanium via an anodic oxidation treatment.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: October 10, 2023
    Assignee: OSONG MEDICAL INNOVATION FOUNDATION
    Inventors: Tae Gon Jung, Yong Hoon Jeong, Su Won Lee, Kwang Min Park, Jae Woong Yang, Jae Young Jung, Kwan Su Kang
  • Patent number: 11776657
    Abstract: A memory device includes a page buffer, a voltage generator, and a test controller. The page buffer is connected to a memory cell through a bit line, and is configured to sense a threshold voltage of the memory cell through a potential of a sensing node electrically connected to the bit line. The voltage generator is configured to generate a test voltage to be applied to the sensing node. The test controller is configured to control the voltage generator to apply the test voltage to the sensing node, and detect a defect of the page buffer, based on a leakage current value of the sensing node.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: October 3, 2023
    Assignee: SK hynix Inc.
    Inventors: In Gon Yang, Tae Ho Kim, Jae Hyeon Shin, Sungmook Lim
  • Publication number: 20230252619
    Abstract: The present disclosure relates to a defect inspection device including: an imaging part that captures an image of a first frame having a predetermined width and a predetermined length along a width direction and a length direction of a test object, respectively; an image division part that divides the image of the first frame of the test object captured by the imaging part into a plurality of second frames smaller than the first frame along the width direction of the test object; a brightness calculation part that measures a brightness value of each of the plurality of the second frames, and calculates a defect determination value of the first frame based on the brightness values of the plurality of the second frames; and a control part that determines a line defect existing along the length direction of the test object based on the calculated defect determination value of the first frame.
    Type: Application
    Filed: July 26, 2021
    Publication date: August 10, 2023
    Inventors: Jae Hyun PARK, Myoung Gon YANG, Kyung Do LEE, Young Woo KO
  • Publication number: 20230187659
    Abstract: A modeling method for designing a flow field of a fuel cell including a membrane electrode assembly including a catalyst layer and an electrolyte membrane, a gas diffusion layer, a flow field, and a bipolar plate includes modeling using a numerical model derived from a governing equation including a mass conservation equation of species, a fluid momentum in a porous media, and a modified Butler-Volmer's equation and outputting an oxygen diffusion characteristic in a catalyst layer from the modeling result.
    Type: Application
    Filed: December 13, 2022
    Publication date: June 15, 2023
    Applicant: KOREA INSTITUTE OF ENERGY RESEARCH
    Inventors: Min Jin KIM, Young Jun SOHN, Hwan Yeong OH, Yoon Young CHOI, Seung Gon KIM, Won Yong LEE, Tae Hyun YANG, Seok Hee PARK, Sung Dae YIM, Seung Hee WOO, Yun Sik KANG, Gu Gon PARK, Eun Jik LEE, So Jeong LEE, Byung Chan BAE, Dong Won SHIN, Hye Jin LEE, Dong Hwan PARK
  • Patent number: 11658307
    Abstract: The present disclosure relates to a method and an apparatus for manufacturing a core-shell catalyst, and more particularly, to a method and an apparatus for manufacturing a core-shell catalyst, in which a particle in the form of a core-shell in which the metal nanoparticle is coated with platinum is manufactured by substituting copper and platinum through a method of manufacturing a metal nanoparticle by emitting a laser beam to a metal ingot, and providing a particular electric potential value, and as a result, it is possible to continuously produce nanoscale uniform core-shell catalysts in large quantities.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: May 23, 2023
    Assignee: KOREA INSTITUTE OF ENERGY RESEARCH
    Inventors: Gu-Gon Park, Sun-Mi Hwang, Sung-Dae Yim, Chang-Soo Kim, Won-Yong Lee, Tae-Hyun Yang, Seok-Hee Park, Minjin Kim, Young-Jun Sohn, Byungchan Bae, Seung-Gon Kim, Dongwon Shin
  • Patent number: 11615847
    Abstract: A memory device includes a plurality of memory cell strings, a peripheral circuit, and control logic. The plurality of memory cell strings are connected between a bit line and a common source line. The peripheral circuit is configured to perform a channel precharge operation and a program operation for the plurality of memory cell strings. The control logic is configured to control the peripheral circuit to apply a pass voltage to a selected word line among a plurality of word lines connected to the plurality of memory cell strings and to apply a turn-on voltage to a source select line connected to the plurality of memory cell strings, during a portion of a period in which the pass voltage is applied to the selected word line, in the program operation.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: March 28, 2023
    Assignee: SK hynix Inc.
    Inventors: Jae Hyeon Shin, In Gon Yang, Sungmook Lim
  • Patent number: 11482286
    Abstract: A memory device capable of reducing a peak current includes a plurality of memory cell strings each including a plurality of memory cells connected between a common source line and a bit line, a source select line connected between the common source line and the plurality of memory cells, and a drain select line connected between the bit line and the plurality of memory cells. A method for operating the memory device includes: precharging channel regions of a plurality of memory cell strings through a common source line; and setting a bit line voltage applied to the bit line, after starting precharging the channel regions of the plurality of memory cell strings, while the channel regions of the plurality of memory cell strings are being precharged.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: October 25, 2022
    Assignee: SK hynix Inc.
    Inventors: Jae Hyeon Shin, Tae Ho Kim, In Gon Yang, Sungmook Lim
  • Patent number: 11462285
    Abstract: The present technology relates to an electronic device. For example, the present technology relates to a memory device and a method of operating the memory device. A memory device according to an embodiment includes a memory cell, a page buffer, and a test performer configured to control the page buffer to sequentially apply a first test voltage and a second test voltage of a level lower than a level of the first test voltage to a sensing node of the page buffer through a bit line, and detect a defect of the sensing node according to whether a potential level of the sensing node is changed.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: October 4, 2022
    Assignee: SK hynix Inc.
    Inventors: Sungmook Lim, In Gon Yang, Jae Hyeon Shin, Hyung Jin Choi
  • Patent number: 11462272
    Abstract: There are provided a memory device and an operating method thereof. The memory device includes: a memory block including a plurality of memory cells and a plurality of select transistors; a peripheral circuit for performing a program operation on selected select transistors among the plurality of select transistors in a select transistor program operation; and a control logic for controlling the peripheral circuit to perform the select transistor program operation. The peripheral circuit applies a coupling voltage having a positive potential to a source line of the memory block in the select transistor program operation.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: October 4, 2022
    Assignee: SK hynix Inc.
    Inventors: Hyung Jin Choi, Jae Hyeon Shin, In Gon Yang, Sungmook Lim
  • Patent number: 11410731
    Abstract: Provided herein is a semiconductor memory device and a method of operating the same. The semiconductor memory device includes a memory block, a peripheral circuit, and a control logic. The memory block includes a plurality of sub-blocks coupled to a plurality of source select lines, respectively. The peripheral circuit performs a program operation on the memory block. The control logic is configured to control the peripheral circuit to increase a voltage of a common source line that is coupled to the memory block, increase a voltage of at least one source select line, among the plurality of source select lines, to a first voltage level, and set a voltage of a bit line that is coupled to the memory block and increase the voltage of at least one source select line from the first voltage level to a second voltage level.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: August 9, 2022
    Assignee: SK hynix Inc.
    Inventors: Jae Hyeon Shin, Tae Ho Kim, In Gon Yang, Sungmook Lim
  • Patent number: 11391678
    Abstract: Provided is a device for detecting a defect of an optical film, comprising a light emitting unit, a reflection unit, a screen, and an image capturing unit, and a method for detecting a defect of an optical film, comprising emitting light to a reflection unit, projecting the light reflected by the reflection unit onto an optical film, capturing an image of a screen which displays a projection shape obtained by projecting the light onto the optical film, and analyzing the image.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: July 19, 2022
    Assignee: SHANJIN OPTOELECTRONICS (SUZHOU) CO., LTD.
    Inventors: Ho Jin Kim, Myoung Gon Yang, Hang Suk Choi, Eung Jin Jang
  • Publication number: 20220216231
    Abstract: Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device may include a stacked body including a plurality of interlayer insulating layers and a plurality of gate electrodes that are alternately stacked on a substrate, and a plurality of channel structures configured to vertically pass through the stacked body. Each of the plurality of channel structures may include a core insulating layer, a first channel layer, a second channel layer, a tunnel insulating layer, and a charge storage layer that extend vertically towards the substrate. Electron mobility of the first channel layer may be higher than electron mobility of the second channel layer.
    Type: Application
    Filed: July 15, 2021
    Publication date: July 7, 2022
    Applicant: SK hynix Inc.
    Inventors: Sungmook LIM, Dae Hwan YUN, Gil Bok CHOI, Jae Hyeon SHIN, In Gon YANG, Hyung Jin CHOI
  • Publication number: 20220139461
    Abstract: There are provided a memory device and an operating method thereof. The memory device includes: a memory block including a plurality of memory cells and a plurality of select transistors; a peripheral circuit for performing a program operation on selected select transistors among the plurality of select transistors in a select transistor program operation; and a control logic for controlling the peripheral circuit to perform the select transistor program operation. The peripheral circuit applies a coupling voltage having a positive potential to a source line of the memory block in the select transistor program operation.
    Type: Application
    Filed: May 7, 2021
    Publication date: May 5, 2022
    Applicant: SK hynix Inc.
    Inventors: Hyung Jin CHOI, Jae Hyeon SHIN, In Gon YANG, Sungmook LIM
  • Publication number: 20220122687
    Abstract: A memory device includes a page buffer, a voltage generator, and a test controller. The page buffer is connected to a memory cell through a bit line, and is configured to sense a threshold voltage of the memory cell through a potential of a sensing node electrically connected to the bit line. The voltage generator is configured to generate a test voltage to be applied to the sensing node. The test controller is configured to control the voltage generator to apply the test voltage to the sensing node, and detect a defect of the page buffer, based on a leakage current value of the sensing node.
    Type: Application
    Filed: April 23, 2021
    Publication date: April 21, 2022
    Applicant: SK hynix Inc.
    Inventors: In Gon YANG, Tae Ho KIM, Jae Hyeon SHIN, Sungmook LIM