Abstract: A semiconductor device may include a page buffer comprising first to fifth latches, wherein the first to third latches and the fifth latch are configured to store 4-bit original data, among 5-bit original data, respectively, and the fourth latch is configured to store data identical with the data that has been stored in the second latch and a control circuit configured to determine a program inhibition pattern based on data that have been stored in two of the first to fifth latches and control the page buffer so that data that has been stored in at least one of the first to fifth latches is inverted based on the program inhibition pattern.

Abstract: The present technology relates to an electronic device. A memory device including a plurality of memory cells connected to a plurality of word lines arranged between a plurality of source select lines and a plurality of drain select lines, a peripheral circuit configured to perform a program operation of programming data in selected memory cells among the plurality of memory cells, and a program operation controller configured to control the peripheral circuit to apply a voltage, for turning on or off source select transistors connected to the plurality of source select lines, to the plurality of source select lines, while applying a pass voltage to the plurality of word lines after applying a program voltage to selected word lines connected to the selected memory cells.

Abstract: A semiconductor device may include a memory cell array including a memory block including a plurality of memory strings connected between a plurality of bit lines and a common source line, a control circuit that generates a page buffer control signal, a voltage control signal, and a drive address signal, a page buffer group including a plurality of page buffers and configured to form each of the plurality of bit lines to a preset voltage level, and generate a threshold voltage variation result on the basis of a change in the voltage level of each of the plurality of bit lines, a voltage generation circuit that generates a threshold verification voltage and a pass voltage, and a line drive circuit that drives a plurality of select lines to a level of the threshold verification voltage, and drives a plurality of word lines to a level of the pass voltage, during the threshold voltage variation verification.

Abstract: A memory device including: a memory device may include: a memory cell array, and a controller configured to perform program loops each comprising a voltage application operation, a word line holding operation, and a verification operation until a program operation for selected memory cells is successful, during the word line holding operation, apply a holding pass voltage having a higher level than a ground voltage to each of first word lines having a program state and second word lines having an erase state, which belong to unselected word lines among a plurality of word lines, during the verification operation, apply a verification pass voltage having a higher level than the holding pass voltage to K word lines that belong to the first word lines and the second word lines, and apply the holding pass voltage to remaining word lines except the K word lines, among the second word lines.

Abstract: A page buffer of a semiconductor memory device includes a bit line connection transistor, an internal operation circuit, and a plurality of latch circuits. During a program operation of selected memory cells, a power voltage is applied to the bit line connection transistor to set a voltage of a bit line connected to memory cells having a threshold voltage greater than a main verify voltage as a program inhibit voltage. In addition, a second program allowable voltage less than the program inhibit voltage is applied to the bit line connection transistor. In addition, a first program allowable voltage less than the second program allowable voltage is applied to the gate of the bit line connection transistor.

Abstract: A memory device comprising: a memory cell array including a plurality of memory cell strings coupled between a plurality of bit lines and a common source line, and a plurality of word lines coupled to the memory cell strings, and a control circuit configured to: repeat a program loop including a program pulse application operation and a verification operation until a program operation is successfully performed on memory cells that are coupled to a selected word line, a selected cell string, and the plurality of bit lines, additionally perform a channel precharge operation together with the program pulse application operation and the verification operation starting from a selected program loop, and vary a level of a precharge voltage applied to the common source line in the channel precharge operation according to an operation temperature.

Abstract: Provided herein may be a semiconductor memory device. The semiconductor memory device may include first and second cell strings. The first cell string is coupled to a first bit line and includes a first drain select transistor, a plurality of memory cells, and a first source select transistor. The second cell string is coupled to the first bit line and includes a second drain select transistor, a plurality of memory cells, and a second source select transistor. A plurality of data bits may be stored in a memory cell group formed by a first memory cell coupled to a first word line among memory cells included in the first cell string, and a second memory cell coupled to the first word line among memory cells included in the second cell string. The number of data bits stored in each of first and second memory cells may be a non-integer.

Abstract: A semiconductor device may include a page buffer comprising first to fifth latches, wherein the first to third latches and the fifth latch are configured to store 4-bit original data, among 5-bit original data, respectively, and the fourth latch is configured to store data identical with the data that has been stored in the second latch and a control circuit configured to determine a program inhibition pattern based on data that have been stored in two of the first to fifth latches and control the page buffer so that data that has been stored in at least one of the first to fifth latches is inverted based on the program inhibition pattern.

Abstract: The present technology relates to a semiconductor device. According to the present technology, a memory device having a reduced size may include a plurality of memory cells connected to a selected word line, a plurality of page buffers configured to store at least one second logical page data except for first logical page data in a plurality of first program loops performed on the plurality of memory cells, and store the first logical page data after the plurality of first program loops are performed, and a control logic configured to control the plurality of first program loops based on the at least one second logical page data, determine first memory cells programmed to one program state based on the first logical page data, and control a plurality of second program loops performed on second memory cells.

Abstract: A semiconductor device may include a memory cell array including a memory block including a plurality of memory strings connected between a plurality of bit lines and a common source line, a control circuit that generates a page buffer control signal, a voltage control signal, and a drive address signal, a page buffer group including a plurality of page buffers and configured to form each of the plurality of bit lines to a preset voltage level, and generate a threshold voltage variation result on the basis of a change in the voltage level of each of the plurality of bit lines, a voltage generation circuit that generates a threshold verification voltage and a pass voltage, and a line drive circuit that drives a plurality of select lines to a level of the threshold verification voltage, and drives a plurality of word lines to a level of the pass voltage, during the threshold voltage variation verification.

Abstract: The present technology relates to an electronic device. A memory device including a plurality of memory cells connected to a plurality of word lines arranged between a plurality of source select lines and a plurality of drain select lines, a peripheral circuit configured to perform a program operation of programming data in selected memory cells among the plurality of memory cells, and a program operation controller configured to control the peripheral circuit to apply a voltage, for turning on or off source select transistors connected to the plurality of source select lines, to the plurality of source select lines, while applying a pass voltage to the plurality of word lines after applying a program voltage to selected word lines connected to the selected memory cells.

Abstract: Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device may include a stacked body including a plurality of interlayer insulating layers and a plurality of gate electrodes that are alternately stacked on a substrate, and a plurality of channel structures configured to vertically pass through the stacked body. Each of the plurality of channel structures may include a core insulating layer, a first channel layer, a second channel layer, a tunnel insulating layer, and a charge storage layer that extend vertically towards the substrate. Electron mobility of the first channel layer may be higher than electron mobility of the second channel layer.

Abstract: A memory device includes a page buffer, a voltage generator, and a test controller. The page buffer is connected to a memory cell through a bit line, and is configured to sense a threshold voltage of the memory cell through a potential of a sensing node electrically connected to the bit line. The voltage generator is configured to generate a test voltage to be applied to the sensing node. The test controller is configured to control the voltage generator to apply the test voltage to the sensing node, and detect a defect of the page buffer, based on a leakage current value of the sensing node.

Abstract: A memory device includes a plurality of memory cell strings, a peripheral circuit, and control logic. The plurality of memory cell strings are connected between a bit line and a common source line. The peripheral circuit is configured to perform a channel precharge operation and a program operation for the plurality of memory cell strings. The control logic is configured to control the peripheral circuit to apply a pass voltage to a selected word line among a plurality of word lines connected to the plurality of memory cell strings and to apply a turn-on voltage to a source select line connected to the plurality of memory cell strings, during a portion of a period in which the pass voltage is applied to the selected word line, in the program operation.

Abstract: A memory device capable of reducing a peak current includes a plurality of memory cell strings each including a plurality of memory cells connected between a common source line and a bit line, a source select line connected between the common source line and the plurality of memory cells, and a drain select line connected between the bit line and the plurality of memory cells. A method for operating the memory device includes: precharging channel regions of a plurality of memory cell strings through a common source line; and setting a bit line voltage applied to the bit line, after starting precharging the channel regions of the plurality of memory cell strings, while the channel regions of the plurality of memory cell strings are being precharged.

Abstract: There are provided a memory device and an operating method thereof. The memory device includes: a memory block including a plurality of memory cells and a plurality of select transistors; a peripheral circuit for performing a program operation on selected select transistors among the plurality of select transistors in a select transistor program operation; and a control logic for controlling the peripheral circuit to perform the select transistor program operation. The peripheral circuit applies a coupling voltage having a positive potential to a source line of the memory block in the select transistor program operation.

Abstract: The present technology relates to an electronic device. For example, the present technology relates to a memory device and a method of operating the memory device. A memory device according to an embodiment includes a memory cell, a page buffer, and a test performer configured to control the page buffer to sequentially apply a first test voltage and a second test voltage of a level lower than a level of the first test voltage to a sensing node of the page buffer through a bit line, and detect a defect of the sensing node according to whether a potential level of the sensing node is changed.

Abstract: Provided herein is a semiconductor memory device and a method of operating the same. The semiconductor memory device includes a memory block, a peripheral circuit, and a control logic. The memory block includes a plurality of sub-blocks coupled to a plurality of source select lines, respectively. The peripheral circuit performs a program operation on the memory block. The control logic is configured to control the peripheral circuit to increase a voltage of a common source line that is coupled to the memory block, increase a voltage of at least one source select line, among the plurality of source select lines, to a first voltage level, and set a voltage of a bit line that is coupled to the memory block and increase the voltage of at least one source select line from the first voltage level to a second voltage level.

Abstract: Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device may include a stacked body including a plurality of interlayer insulating layers and a plurality of gate electrodes that are alternately stacked on a substrate, and a plurality of channel structures configured to vertically pass through the stacked body. Each of the plurality of channel structures may include a core insulating layer, a first channel layer, a second channel layer, a tunnel insulating layer, and a charge storage layer that extend vertically towards the substrate. Electron mobility of the first channel layer may be higher than electron mobility of the second channel layer.

Abstract: There are provided a memory device and an operating method thereof. The memory device includes: a memory block including a plurality of memory cells and a plurality of select transistors; a peripheral circuit for performing a program operation on selected select transistors among the plurality of select transistors in a select transistor program operation; and a control logic for controlling the peripheral circuit to perform the select transistor program operation. The peripheral circuit applies a coupling voltage having a positive potential to a source line of the memory block in the select transistor program operation.