Patents by Inventor In Gon YANG
In Gon YANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220068388Abstract: A memory device capable of reducing a peak current includes a plurality of memory cell strings each including a plurality of memory cells connected between a common source line and a bit line, a source select line connected between the common source line and the plurality of memory cells, and a drain select line connected between the bit line and the plurality of memory cells. A method for operating the memory device includes: precharging channel regions of a plurality of memory cell strings through a common source line; and setting a bit line voltage applied to the bit line, after starting precharging the channel regions of the plurality of memory cell strings, while the channel regions of the plurality of memory cell strings are being precharged.Type: ApplicationFiled: March 3, 2021Publication date: March 3, 2022Applicant: SK hynix Inc.Inventors: Jae Hyeon SHIN, Tae Ho KIM, In Gon YANG, Sungmook LIM
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Publication number: 20220059167Abstract: A memory device includes a plurality of memory cell strings, a peripheral circuit, and control logic, The plurality of memory cell strings are connected between a bit line and a common source line. The peripheral circuit is configured to perform a channel precharge operation and a program operation for the plurality of memory cell strings. The control logic is configured to control the peripheral circuit to apply a pass voltage to a selected word line among a plurality of word lines connected to the plurality of memory cell strings and to apply a turn-on voltage to a source select line connected to the plurality of memory cell strings, during a portion of a period in which the pass voltage is applied to the selected word line, in the program operation.Type: ApplicationFiled: February 23, 2021Publication date: February 24, 2022Applicant: SK hynix Inc.Inventors: Jae Hyeon SHIN, In Gon YANG, Sungmook LIM
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Publication number: 20220051723Abstract: Provided herein is a semiconductor memory device and a method of operating the same, The semiconductor memory device includes a memory block, a peripheral circuit, and a control logic. The memory block includes a plurality of sub-blocks coupled to a plurality of source select lines, respectively. The peripheral circuit performs a program operation on the memory block. The control logic is configured to control the peripheral circuit to increase a voltage of a common source line that is coupled to the memory block, increase a voltage of at least one source select line, among the plurality of source select lines, to a first voltage level, and set a voltage of a bit line that is coupled to the memory block and increase the voltage of at least one source select line from the first voltage level to a second voltage level.Type: ApplicationFiled: February 16, 2021Publication date: February 17, 2022Applicant: SK hynix Inc.Inventors: Jae Hyeon SHIN, Tae Ho KIM, In Gon YANG, Sungmook LIM
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Patent number: 11150201Abstract: The present disclosure relates to a system and a method of detecting a defect of an optical film, and more particularly, to a system and a method of detecting a defect of an optical film, which obtain an image of a defect of an optical film projected onto a screen and detect the defect of the optical film. As an exemplary embodiment of the present disclosure, a system for detecting a defect of an optical film may be provided.Type: GrantFiled: March 23, 2017Date of Patent: October 19, 2021Assignee: SHANJIN OPTOELECTRONICS (SUZHOU) CO., LTD.Inventors: Ho Jin Kim, Myoung Gon Yang, Chang Seok Park, Je Hyun Kim, Hang Suk Choi
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Patent number: 11017861Abstract: Provided herein may be a semiconductor memory device and a method of operating the semiconductor memory device to program a selected physical page of the semiconductor memory device. The method may include performing a plurality of program loops. Each of the program loops may include: applying a bit line voltage based on data input to a page buffer of the semiconductor memory device; applying a two-step program pulse to a word line coupled to the selected physical page; performing a program verify operation on the selected physical page using a double verify scheme; and determining a bit line voltage to be applied in a subsequent program loop based on a result of the program verify operation.Type: GrantFiled: December 15, 2020Date of Patent: May 25, 2021Assignee: SK hynix Inc.Inventor: In Gon Yang
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Publication number: 20210098066Abstract: Provided herein may be a semiconductor memory device and a method of operating the semiconductor memory device to program a selected physical page of the semiconductor memory device. The method may include performing a plurality of program loops. Each of the program loops may include: applying a bit line voltage based on data input to a page buffer of the semiconductor memory device; applying a two-step program pulse to a word line coupled to the selected physical page; performing a program verify operation on the selected physical page using a double verify scheme; and determining a bit line voltage to be applied in a subsequent program loop based on a result of the program verify operation.Type: ApplicationFiled: December 15, 2020Publication date: April 1, 2021Inventor: In Gon YANG
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Publication number: 20210050051Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a memory cell array, a plurality of page buffer groups, and a program operation controller. The memory cell array may include a plurality of memory cells. The page buffer groups may be coupled to the plurality of memory cells through a plurality of bit line groups, and may be configured to perform bit line precharge operations on the plurality of bit line groups. The program operation controller may be configured to control the plurality of page buffer groups to perform the bit line precharge operations initiated at different time points during a program operation on the plurality of memory cells, and to adjust an interval between initiation time points of the bit line precharge operations depending on a progress of the program operation.Type: ApplicationFiled: April 23, 2020Publication date: February 18, 2021Applicant: SK hynix Inc.Inventor: In Gon YANG
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Patent number: 10896734Abstract: Provided herein may be a semiconductor memory device and a method of operating the semiconductor memory device to program a selected physical page of the semiconductor memory device. The method may include performing a plurality of program loops. Each of the program loops may include: applying a bit line voltage based on data input to a page buffer of the semiconductor memory device; applying a two-step program pulse to a word line coupled to the selected physical page; performing a program verify operation on the selected physical page using a double verify scheme; and determining a bit line voltage to be applied in a subsequent program loop based on a result of the program verify operation.Type: GrantFiled: July 30, 2018Date of Patent: January 19, 2021Assignee: SK hynix Inc.Inventor: In Gon Yang
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Publication number: 20200232932Abstract: Provided is a device for detecting a defect of an optical film, comprising a light emitting unit, a reflection unit, a screen, and an image capturing unit, and a method for detecting a defect of an optical film, comprising emitting light to a reflection unit, projecting the light reflected by the reflection unit onto an optical film, capturing an image of a screen which displays a projection shape obtained by projecting the light onto the optical film, and analyzing the image.Type: ApplicationFiled: July 27, 2018Publication date: July 23, 2020Inventors: Ho Jin KIM, Myoung Gon YANG, Hang Suk CHOI, Eung Jin JANG
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Publication number: 20200209167Abstract: The present disclosure relates to a system and a method of detecting a defect of an optical film, and more particularly, to a system and a method of detecting a defect of an optical film, which obtain an image of a defect of an optical film projected onto a screen and detect the defect of the optical film. As an exemplary embodiment of the present disclosure, a system for detecting a defect of an optical film may be provided.Type: ApplicationFiled: March 23, 2017Publication date: July 2, 2020Inventors: Ho Jin KIM, Myoung Gon YANG, Chang Seok PARK, Je Hyun KIM, Hang Suk CHOI
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Publication number: 20190189215Abstract: Provided herein may be a semiconductor memory device and a method of operating the semiconductor memory device to program a selected physical page of the semiconductor memory device. The method may include performing a plurality of program loops. Each of the program loops may include: applying a bit line voltage based on data input to a page buffer of the semiconductor memory device; applying a two-step program pulse to a word line coupled to the selected physical page; performing a program verify operation on the selected physical page using a double verify scheme; and determining a bit line voltage to be applied in a subsequent program loop based on a result of the program verify operation.Type: ApplicationFiled: July 30, 2018Publication date: June 20, 2019Inventor: In Gon YANG
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Patent number: 9990969Abstract: Provided herein are a page buffer and a memory device having the same. The page buffer may include: a latch circuit comprising a first node configured to be set to a first level in response to a sense amplifier strobe signal when an operation of setting up a bit line is performed during a program operation of a semiconductor memory device; a current control circuit configured to supply an internal power to a current sensing node depending on a value of the first level of the first node; and a page buffer sensing circuit configured to couple the bit line to the current sensing node in response to a page buffer sensing signal and control a potential level of the bit line depending on a potential level of the page buffer sensing signal.Type: GrantFiled: November 14, 2016Date of Patent: June 5, 2018Assignee: SK Hynix Inc.Inventor: In Gon Yang
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Publication number: 20170358335Abstract: Provided herein are a page buffer and a memory device having the same. The page buffer may include: a latch circuit comprising a first node configured to be set to a first level in response to a sense amplifier strobe signal when an operation of setting up a bit line is performed during a program operation of a semiconductor memory device; a current control circuit configured to supply an internal power to a current sensing node depending on a value of the first level of the first node; and a page buffer sensing circuit configured to couple the bit line to the current sensing node in response to a page buffer sensing signal and control a potential level of the bit line depending on a potential level of the page buffer sensing signal.Type: ApplicationFiled: November 14, 2016Publication date: December 14, 2017Inventor: In Gon YANG
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Patent number: 9230675Abstract: A semiconductor memory device is disclosed. The semiconductor memory device includes a current mirror configured to include a current mirror section for current of a first line to a second line and transistors coupled in parallel, a detector configured to control a voltage of the first line based on voltages of sensing nodes, a fail bit set section configured to control a voltage of the second line, and a comparator configured to compare the voltage of the first line with the voltage of the second line and generate a pass and fail check signal based on the comparing result.Type: GrantFiled: June 19, 2015Date of Patent: January 5, 2016Assignee: SK HYNIX INC.Inventors: In Gon Yang, Sung Hoon Ahn
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Publication number: 20150287470Abstract: A semiconductor memory device is disclosed. The semiconductor memory device includes a current mirror configured to include a current mirror section for current of a first line to a second line and transistors coupled in parallel, a detector configured to control a voltage of the first line based on voltages of sensing nodes, a fail bit set section configured to control a voltage of the second line, and a comparator configured to compare the voltage of the first line with the voltage of the second line and generate a pass and fail check signal based on the comparing result.Type: ApplicationFiled: June 19, 2015Publication date: October 8, 2015Inventors: In Gon YANG, Sung Hoon Ahn
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Patent number: 9093124Abstract: A semiconductor memory device is disclosed. The semiconductor memory device includes a current mirror configured to include a current mirror section for current of a first line to a second line and transistors coupled in parallel, a detector configured to control a voltage of the first line based on voltages of sensing nodes, a fail bit set section configured to control a voltage of the second line, and a comparator configured to compare the voltage of the first line with the voltage of the second line and generate a pass and fail check signal based on the comparing result.Type: GrantFiled: December 18, 2012Date of Patent: July 28, 2015Assignee: SK Hynix Inc.Inventors: In Gon Yang, Sung Hoon Ahn
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Patent number: 8902674Abstract: A semiconductor memory device includes a memory cell array configured to include memory cells, peripheral circuits configured to read out data stored in a selected memory cell in a read operation, and a controller configured to control the peripheral circuits so that the peripheral circuits sense a voltage level of the bit line when a first read voltage of the read voltages is supplied to the word line and the peripheral circuits sense voltage levels of the bit line when a second read voltage lower than the first read voltage by a specific level and a third read voltage higher than the first read voltage by the specific level are supplied to the word line in order to determine whether a threshold voltage of the selected memory cell falls within a set voltage distribution in the read operation.Type: GrantFiled: April 19, 2012Date of Patent: December 2, 2014Assignee: SK Hynix Inc.Inventors: In Gon Yang, Duck Ju Kim, Jae Won Cha, Sung Hoon Ahn, Tae Ho Jeon
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Publication number: 20140056083Abstract: A semiconductor memory device is disclosed. The semiconductor memory device includes a current mirror configured to include a current mirror section for current of a first line to a second line and transistors coupled in parallel, a detector configured to control a voltage of the first line based on voltages of sensing nodes, a fail bit set section configured to control a voltage of the second line, and a comparator configured to compare the voltage of the first line with the voltage of the second line and generate a pass and fail check signal based on the comparing result.Type: ApplicationFiled: December 18, 2012Publication date: February 27, 2014Applicant: SK hynix Inc.Inventors: In Gon Yang, Sung Hoon Ahn
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Publication number: 20120269007Abstract: A semiconductor memory device includes a memory cell array configured to include memory cells, peripheral circuits configured to read out data stored in a selected memory cell in a read operation, and a controller configured to control the peripheral circuits so that the peripheral circuits sense a voltage level of the bit line when a first read voltage of the read voltages is supplied to the word line and the peripheral circuits sense voltage levels of the bit line when a second read voltage lower than the first read voltage by a specific level and a third read voltage higher than the first read voltage by the specific level are supplied to the word line in order to determine whether a threshold voltage of the selected memory cell falls within a set voltage distribution in the read operation.Type: ApplicationFiled: April 19, 2012Publication date: October 25, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventors: In Gon YANG, Duck Ju KIM, Jae Won CHA, Sung Hoon AHN, Tae Ho JEON
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Publication number: 20050145774Abstract: The present invention relates to an apparatus and a method for operating and controlling a display and a backlight in the portable terminals, and more particularly, to an apparatus and a method for controlling the backlight and the display without a key input. The present invention the steps of: generating a sensing signal and transmitting the sensing signal to a control means, wherein the sensing signal is issued by an action taken by a user; receiving the sensing signal in the control means and generating a control signal; and turning on a backlight in response to the control signal. Accordingly, an unnecessary key input is removed in turning on the backlight and in rotating the output pattern of the phone.Type: ApplicationFiled: June 10, 2004Publication date: July 7, 2005Inventors: Ki-Gon Yang, Jeffrey-Han Kang, Ki-Yeong Shin, Hyun-Chul Park