Abstract: Provided herein may be a semiconductor memory device including a memory cell, a read and write circuit, a current sensing circuit, and control logic. The memory cell array includes a plurality of memory cells. The read and write circuit includes a plurality of page buffers coupled to the plurality of memory cells through a plurality of bit lines, respectively. The current sensing circuit is coupled to the read and write circuit through a plurality of sensing lines. The control logic is configured to control operations of the current sensing circuit and the read and write circuit. At least two page buffers among the plurality of page buffers are coupled to one of the plurality of sensing lines. The control logic controls the read and write circuit to simultaneously perform a current sensing operation for the at least two page buffers.

Abstract: An antenna module includes a connection member including at least one wiring layer and at least one insulating layer; an integrated circuit (IC) package disposed on a first surface of the connection member; and an antenna package including a plurality of antenna members and a plurality of feed vias, and disposed on a second surface of the connection member, wherein the IC package includes: an IC having an active surface electrically connected to at least one wiring layer and an inactive surface opposing the active surface, and generating the RF signal; a heat sink member disposed on the inactive surface of the IC; and an encapsulant encapsulating at least portions of the IC and the heat sink member.

Abstract: Disclosed is a semiconductor light emitting device including: a body with a bottom part having at least one hole formed therein; a semiconductor light emitting device chip to be placed in each of the at least one hole, with the semiconductor light emitting device chip being comprised of a plurality of semiconductor layers including an active layer for generating light by electron-hole recombination, and an electrode electrically connected to the plurality of semiconductor layers; and an encapsulating member for covering the semiconductor light emitting device chip, wherein a hole—defining inner face of the bottom part has a plurality of angles of inclination.

Abstract: There are provided a fan-out sensor package and an optical fingerprint sensor module including the same. The fan-out sensor package includes: a connection member having a 5 through-hole; an image sensor disposed in the through-hole of the connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the connection member, the image sensor, and 10 an optical lens; and a redistribution layer disposed on the connection member, the image sensor, and the optical lens. The connection member includes a wiring layer, and the redistribution layer electrically connects the wiring layer and the connection pads to each other.

Abstract: An antenna module includes a connection member including at least one wiring layer and at least one insulating layer; an integrated circuit (IC) disposed on a first surface of the connection member and electrically connected to at least one wiring layer; and an antenna package disposed on a second surface of the connection member, and including a dielectric layer, a plurality of antenna members, and a plurality of feed vias, wherein the antenna package further includes a chip antenna including a dielectric body and first and second electrodes, respectively disposed on first and second surfaces of the dielectric body, wherein the chip antenna is disposed to be spaced apart from the plurality of feed vias within the dielectric layer so that at least one of the first electrode or the second electrode is electrically connected to a corresponding wire of the at least one wiring layer.

Abstract: Disclosed is a method of fabricating a resistive switching memory. A method of fabricating a resistive switching memory according to an embodiment of the present invention includes a step of forming a lower electrode on a substrate; a step of forming a resistive switching layer on the lower electrode using sputtering; and a step of forming an upper electrode on the resistive switching layer, wherein, in the step of forming a resistive switching layer on the lower electrode using sputtering, the substrate is disposed in a region, which is not reached by plasma generated by the first and second targets, between the first target and the second target disposed above the substrate to deposit the resistive switching layer.

Abstract: The present technology relates to a memory device and method of operating the memory device. The memory device includes a plurality of memory cells, a peripheral circuit, and control logic. The peripheral circuit performs a plurality of program loops each including a program operation and a verify operation on selected memory cells of the plurality of memory cells. The control logic controls the peripheral circuit to increase a potential of selected bit lines.

Abstract: Apparatuses, systems, and methods for a wireless device to perform methods for de-registration of the wireless device from a first access type over a second access type. Methods also include procedures for maintaining state machines associated with both access types as well as procedures to determine a connection for re-transmitting a de-registration request and to avoid collisions between procedures associated with the first and second access types. Further, methods include an information element configured to indicate which access type has been de-registered.

Abstract: A memory device includes: a memory block, coupled to a plurality of word lines; a peripheral circuit for performing a sensing operation on selected memory cells of the memory block, the select memory cells being coupled to a selected word line of the plurality of word lines; a word line voltage controller for controlling a sensing voltage applied to the selected word line to perform the sensing operation on the selected memory cells and configured to control a pass voltage applied to the selected word line and unselected word lines of the plurality of word lines, coupled to the memory block; and a bit line control signal generator for controlling the peripheral circuit to apply a channel precharge voltage to respective bit lines, coupled to the selected memory cells, while the pass voltage is being applied to the selected word line and the unselected word lines.

Abstract: A board includes: a core structure; one or more first passive components embedded in the core structure; a first build-up structure disposed on one side of the core structure and including first build-up layers and first wiring layers; and a second build-up structure disposed on the other side of the core structure and including second build-up layers and second wiring layers. One surface of a first core layer contacting a first insulating layer is coplanar with one surface of each of the one or more first passive components contacting a first insulating layer, the other surface of each of the one or more first passive components covered with a second insulating layer is spaced apart from a second core layer, and the one or more first passive components are electrically connected to at least one of the plurality of first wiring layers and the plurality of second wiring layers.

Abstract: An antenna module includes a first connection member including at least one first wiring layer and at least one first insulating layer; an antenna package disposed on a first surface of the first connection member, and including a plurality of antenna members and a plurality of feed vias; an integrated circuit (IC) disposed on a second surface of the first connection member and electrically connected to the corresponding wire of at least one first wiring layer; and a second connection member including at least one second wiring layer electrically connected to the IC and at least one second insulating layer, and disposed between the first connection member and the IC, wherein the second connection member has a third surface facing the first connection member and having an area smaller than that of the second surface, and a fourth surface facing the IC.

Abstract: Techniques are disclosed relating to handover of WLAN voice calls to one or more cellular networks. In some embodiments, a device is configured to perform voice communications over one or more wireless local area networks, communicate with a first network using a first cellular radio access technology (RAT), and communicate with a second network using a second cellular RAT. The device may store, based on communications via the first network, information indicating that the first network does not support voice communications for the apparatus. The device may handover a voice call from a wireless local network directly to the second cellular RAT, based on the stored information and without handover of the voice call to the first cellular RAT, based on call conditions on the wireless local area network.

Abstract: Disclosed are a switching atomic transistor with a diffusion barrier layer and a method of operating the same. By introducing a diffusion barrier layer in an intermediate layer having a resistance change characteristic, it is possible to minimize variation in the entire number of ions in the intermediate layer involved in operation of the switching atomic transistor or to eliminate the variation to maintain stable operation of the switching atomic transistor. In addition, it is possible to stably implement a multi-level cell of a switching atomic transistor capable of storing more information without increasing the number of memory cells. Also, disclosed are a vertical atomic transistor with a diffusion barrier layer and a method of operating the same. By producing an ion channel layer in a vertical structure, it is possible to significantly increase transistor integration.

Abstract: Apparatuses, systems, and methods for a user equipment device (UE) to perform methods for enhancement of multi-SIM devices, such as UE 106. A network may increase paging retries for known MU-SIM devices, e.g., based on an indication of capabilities from a MU-SIM device. The indication may be via a NAS registration request, an RRC capability procedure, and/or an RRC UE assistance procedure. Additionally, a network may include an indication of a paging priority to the UE. The UE may then determine a response to the page based, at least in part, on the indicated priority. Further, the UE may indicate a tune-away to the network. The indication of the tune-away may include a cause and/or duration for the tune-away and may be provided at an RRC level or a network access stratum (NAS) level.

Abstract: Provided herein are a page buffer, a memory device having the page buffer, and a method of operating the memory device. The memory device includes a voltage generator configured to generate operating voltages for operating a plurality of memory cells, a program and verify circuit configured to apply the operating voltages to word lines and bit lines coupled to the memory cells and to perform a program operation and a verify operation, and a program operation controller configured to control the program and verify circuit and the voltage generator so that a bit line precharge operation is performed and so that, when the bit line precharge operation has been completed, a bit line discharge operation is performed.

Abstract: An antenna substrate includes: a first substrate including an antenna pattern disposed on an upper surface of the first substrate; a second substrate having a first planar surface, an area of which is smaller than an area of a planar surface of the first substrate; and a flexible substrate connecting the first and second substrates to each other and bent to allow the first planar surface of the second substrate to face a side surface of the first substrate, which is perpendicular to the upper surface of the first substrate.

Abstract: A printed circuit board includes a coreless substrate including an insulating body and a plurality of core wiring layers disposed on or within the insulating body, a build-up insulating layer covering at least a portion of each of an upper surface and a lower surface of the coreless substrate, and a build-up wiring layer disposed on at least one of an upper surface and a lower surface of the build-up insulating layer. A through-opening penetrates through the insulating body and is configured to receive an electronic component therein, and the first build-up insulating layer extends into the through-opening to embed the electronic component.

Abstract: A semiconductor memory device operates by applying a program pulse to a selected word line, updating a program pulse count value, determining a current sensing mode based upon the program pulse count value, and performing a program verify operation based upon the current sensing mode. The current sensing mode is determined by determining one of an individual state current sensing operation for determining verify pass or fail for one target program state and an all-state current sensing operation for determining verify pass or fail for all target program states.

Abstract: Disclosed is a method for manufacturing a semiconductor light emitting device, the method including: providing a mask having a plurality of openings on a base; placing semiconductor light emitting chips on exposed portions of the base through the openings, respectively, by a device carrier which recognizes a shape of the mask and calibrates position for a semiconductor light emitting chip to be seated; and supplying an encapsulant to each of the openings, with the mask serving as a dam.

Abstract: Disclosed are a switching atomic transistor with a diffusion barrier layer and a method of operating the same. By introducing a diffusion barrier layer in an intermediate layer having a resistance change characteristic, it is possible to minimize variation in the entire number of ions in the intermediate layer involved in operation of the switching atomic transistor or to eliminate the variation to maintain stable operation of the switching atomic transistor. In addition, it is possible to stably implement a multi-level cell of a switching atomic transistor capable of storing more information without increasing the number of memory cells. Also, disclosed are a vertical atomic transistor with a diffusion barrier layer and a method of operating the same. By producing an ion channel layer in a vertical structure, it is possible to significantly increase transistor integration.