Patents by Inventor In Ho RHA
In Ho RHA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230307371Abstract: A semiconductor memory device includes a peripheral circuit structure including a peripheral circuit substrate, a peripheral circuit element on the peripheral circuit substrate, and a wiring structure connected to the peripheral circuit element and a memory cell structure provided on the peripheral circuit structure. The memory cell structure includes a cell substrate including a cell array region, an extended region, and a through region, a mold structure including a plurality of gate electrodes sequentially provided on the cell array region and on the extended region in a step form, and a plurality of mold sacrifice films sequentially provided on the through region, a channel structure intersecting the plurality of gate electrodes on the cell array region, and a cell contact penetrating the mold structure on the extended region and configured to connect at least one of the plurality of gate electrodes and the wiring structure.Type: ApplicationFiled: November 4, 2022Publication date: September 28, 2023Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji Youn SEO, Sang Ho RHA, Tae-Jong HAN
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Patent number: 11700731Abstract: A method of manufacturing a vertical memory device includes forming a first sacrificial layer on a substrate, the first sacrificial layer including a first insulating material, forming a mold including an insulation layer and a second sacrificial layer alternately and repeatedly stacked on the first sacrificial layer, the insulation layer and the second sacrificial layer including second and third insulating materials, respectively, different from the first insulating material, forming a channel through the mold and the first sacrificial layer, forming an opening through the mold and the first sacrificial layer to expose an upper surface of the substrate, removing the first sacrificial layer through the opening to form a first gap, forming a channel connecting pattern to fill the first gap, and replacing the second sacrificial layer with a gate electrode.Type: GrantFiled: June 15, 2021Date of Patent: July 11, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Il-Woo Kim, Sang-Ho Rha, Byoung-Deog Choi, Ik-Soo Kim, Min-Jae Oh
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Publication number: 20230146542Abstract: A semiconductor memory device includes a cell substrate, a mold structure including a plurality of gate electrodes stacked on the cell substrate, the gate electrodes including a first ground selection line, a second ground selection line and a plurality of word lines, which are sequentially stacked, a channel structure that extends in a vertical direction that crosses an upper surface of the cell substrate and penetrates the mold structure, a partial isolation region that extends in a first direction that is parallel with the upper surface of the cell substrate and partially separates the mold structure, and a ground isolation structure that connects two partial isolation regions adjacent to each other in the first direction, extends in the vertical direction and penetrates the first ground selection line and the second ground selection line, wherein a width of the ground isolation structure increases with distance from the cell substrate.Type: ApplicationFiled: May 31, 2022Publication date: May 11, 2023Inventors: Min Jae OH, Ik Soo KIM, Sang Ho RHA, Ji Woon IM
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Publication number: 20210313347Abstract: A method of manufacturing a vertical memory device includes forming a first sacrificial layer on a substrate, the first sacrificial layer including a first insulating material, forming a mold including an insulation layer and a second sacrificial layer alternately and repeatedly stacked on the first sacrificial layer, the insulation layer and the second sacrificial layer including second and third insulating materials, respectively, different from the first insulating material, forming a channel through the mold and the first sacrificial layer, forming an opening through the mold and the first sacrificial layer to expose an upper surface of the substrate, removing the first sacrificial layer through the opening to form a first gap, forming a channel connecting pattern to fill the first gap, and replacing the second sacrificial layer with a gate electrode.Type: ApplicationFiled: June 15, 2021Publication date: October 7, 2021Inventors: Il-Woo KIM, Sang-Ho RHA, Byoung-Deog CHOI, Ik-Soo KIM, Min-Jae OH
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Patent number: 11107681Abstract: A method of fabricating a semiconductor device and a semiconductor processing apparatus are provided. The method of fabricating a semiconductor device comprises preparing a semiconductor substrate having a front side and a back side, opposing each other, and forming a material layer on the semiconductor substrate. The material layer is formed on at least a portion of the back side of the semiconductor substrate while being formed on the front side of the semiconductor substrate. The material layer formed on the at least a portion of the back side of the semiconductor substrate is removed, while the material layer formed on the front side of the semiconductor substrate remains. A semiconductor process is performed to fabricate the semiconductor device using the material layer remaining on the front side of the semiconductor substrate.Type: GrantFiled: September 20, 2019Date of Patent: August 31, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji Youn Seo, Ji Woon Im, Dai Hong Kim, Ik Soo Kim, Sang Ho Rha
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Patent number: 11063060Abstract: A method of manufacturing a vertical memory device includes forming a first sacrificial layer on a substrate, the first sacrificial layer including a first insulating material, forming a mold including an insulation layer and a second sacrificial layer alternately and repeatedly stacked on the first sacrificial layer, the insulation layer and the second sacrificial layer including second and third insulating materials, respectively, different from the first insulating material, forming a channel through the mold and the first sacrificial layer, forming an opening through the mold and the first sacrificial layer to expose an upper surface of the substrate, removing the first sacrificial layer through the opening to form a first gap, forming a channel connecting pattern to fill the first gap, and replacing the second sacrificial layer with a gate electrode.Type: GrantFiled: June 27, 2019Date of Patent: July 13, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Il-Woo Kim, Sang-Ho Rha, Byoung-Deog Choi, Ik-Soo Kim, Min-Jae Oh
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Publication number: 20200211847Abstract: A method of fabricating a semiconductor device and a semiconductor processing apparatus are provided. The method of fabricating a semiconductor device comprises preparing a semiconductor substrate having a front side and a back side, opposing each other, and forming a material layer on the semiconductor substrate. The material layer is formed on at least a portion of the back side of the semiconductor substrate while being formed on the front side of the semiconductor substrate. The material layer formed on the at least a portion of the back side of the semiconductor substrate is removed, while the material layer formed on the front side of the semiconductor substrate remains. A semiconductor process is performed to fabricate the semiconductor device using the material layer remaining on the front side of the semiconductor substrate.Type: ApplicationFiled: September 20, 2019Publication date: July 2, 2020Inventors: Ji Youn SEO, Ji Woon IM, Dai Hong KIM, Ik Soo KIM, Sang Ho RHA
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Publication number: 20200135760Abstract: A method of manufacturing a vertical memory device includes forming a first sacrificial layer on a substrate, the first sacrificial layer including a first insulating material, forming a mold including an insulation layer and a second sacrificial layer alternately and repeatedly stacked on the first sacrificial layer, the insulation layer and the second sacrificial layer including second and third insulating materials, respectively, different from the first insulating material, forming a channel through the mold and the first sacrificial layer, forming an opening through the mold and the first sacrificial layer to expose an upper surface of the substrate, removing the first sacrificial layer through the opening to form a first gap, forming a channel connecting pattern to fill the first gap, and replacing the second sacrificial layer with a gate electrode.Type: ApplicationFiled: June 27, 2019Publication date: April 30, 2020Inventors: Il-Woo KIM, Sang-Ho RHA, Byoung-Deog CHOI, Ik-Soo KIM, Min-Jae OH
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Patent number: 10379643Abstract: The present invention provides an electrode structure for a touch panel and a method for fabricating the same, in which a unit wire and another unit wire continued thereto are continued while the contact area between the unit wires decreases from the entire line width, thereby achieving irregular patterns. In the electrode structure for the touch panel and the method for fabricating the same, a metal wire formed with continuous unit wires has an irregular pattern where the contact area between any one unit wire and another unit wire continued thereto decreases, from the entire line width, by a non-contact size value k obtained by dividing a line width by an arbitrary real number.Type: GrantFiled: June 30, 2015Date of Patent: August 13, 2019Assignee: DONGWOO FINE-CHEM CO., LTD.Inventors: Changjun Maeng, Myunsoo Kim, In Ho Rha, Woo Hyun Bae
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Publication number: 20170147099Abstract: The present invention provides an electrode structure for a touch panel and a method for fabricating the same, in which a unit wire and another unit wire continued thereto are continued while the contact area between the unit wires decreases from the entire line width, thereby achieving irregular patterns. In the electrode structure for the touch panel and the method for fabricating the same, a metal wire formed with continuous unit wires has an irregular pattern where the contact area between any one unit wire and another unit wire continued thereto decreases, from the entire line width, by a non-contact size value k obtained by dividing a line width by an arbitrary real number.Type: ApplicationFiled: June 30, 2015Publication date: May 25, 2017Applicant: DONGWOO FINE-CHEM CO., LTD.Inventors: Changjun MAENG, Myunsoo KIM, In Ho RHA, Woo Hyun BAE
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Patent number: 9390966Abstract: Methods of forming a wiring structure are provided including forming an insulating interlayer on a substrate and forming a sacrificial layer on the insulating interlayer. The sacrificial layer is partially removed to define a plurality of openings. Wiring patterns are formed in the openings. The sacrificial layer is transformed into a modified sacrificial layer by a plasma treatment. The modified sacrificial layer is removed by a wet etching process. An insulation layer covering the wiring patterns is formed on the insulating interlayer. The insulation layer defines an air gap therein between neighboring wiring patterns.Type: GrantFiled: October 17, 2014Date of Patent: July 12, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Woo-Kyung You, Sang-Ho Rha, Jong-Min Baek, Sang-Hoon Ahn, Nae-In Lee
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Publication number: 20160133577Abstract: A wiring structure includes a first insulation layer, a plurality of wiring patterns, a protection layer pattern and a second insulation layer. The first insulation layer may be formed on a substrate. A plurality of wiring patterns may be formed on the first insulation layer, and each of the wiring patterns may include a metal layer pattern and a barrier layer pattern covering a sidewall and a bottom surface of the metal layer pattern. The protection layer pattern may cover a top surface of each of the wiring patterns and including a material having a high reactivity with respect to oxygen. The protection layer pattern may cover a top surface of each of the wiring patterns and including a material having a high reactivity with respect to oxygen.Type: ApplicationFiled: January 19, 2016Publication date: May 12, 2016Inventors: Jong-Min Baek, Sang-Ho Rha, Woo-Kyung You, Sang-Hoon Ahn, Nae-In Lee, Ki-Chul Kim, Jeon-Il Lee
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Patent number: 9281277Abstract: A wiring structure includes a first insulation layer, a plurality of wiring patterns, a protection layer pattern and a second insulation layer. The first insulation layer may be formed on a substrate. A plurality of wiring patterns may be formed on the first insulation layer, and each of the wiring patterns may include a metal layer pattern and a barrier layer pattern covering a sidewall and a bottom surface of the metal layer pattern. The protection layer pattern may cover a top surface of each of the wiring patterns and including a material having a high reactivity with respect to oxygen. The protection layer pattern may cover a top surface of each of the wiring patterns and including a material having a high reactivity with respect to oxygen.Type: GrantFiled: October 30, 2014Date of Patent: March 8, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Min Baek, Sang-Ho Rha, Woo-Kyung You, Sang-Hoon Ahn, Nae-In Lee, Ki-Chul Kim, Jeon-Il Lee
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Publication number: 20150194333Abstract: Methods of forming a wiring structure are provided including forming an insulating interlayer on a substrate and forming a sacrificial layer on the insulating interlayer. The sacrificial layer is partially removed to define a plurality of openings. Wiring patterns are formed in the openings. The sacrificial layer is transformed into a modified sacrificial layer by a plasma treatment. The modified sacrificial layer is removed by a wet etching process. An insulation layer covering the wiring patterns is formed on the insulating interlayer. The insulation layer defines an air gap therein between neighboring wiring patterns.Type: ApplicationFiled: October 17, 2014Publication date: July 9, 2015Inventors: Woo-Kyung You, Sang-Ho Rha, Jong-Min Baek, Sang-Hoon Ahn, Nae-In Lee
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Publication number: 20150179582Abstract: A wiring structure includes a first insulation layer, a plurality of wiring patterns, a protection layer pattern and a second insulation layer. The first insulation layer may be formed on a substrate. A plurality of wiring patterns may be formed on the first insulation layer, and each of the wiring patterns may include a metal layer pattern and a barrier layer pattern covering a sidewall and a bottom surface of the metal layer pattern. The protection layer pattern may cover a top surface of each of the wiring patterns and including a material having a high reactivity with respect to oxygen. The protection layer pattern may cover a top surface of each of the wiring patterns and including a material having a high reactivity with respect to oxygen.Type: ApplicationFiled: October 30, 2014Publication date: June 25, 2015Inventors: Jong-Min Baek, Sang-Ho Rha, Woo-Kyung You, Sang-Hoon Ahn, Nae-In Lee, Ki-Chul Kim, Jeon-II Lee
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Patent number: 7781304Abstract: A semiconductor device having a trench isolation region and methods of fabricating the same are provided. The method includes forming a first trench region in a substrate, and a second trench region having a larger width than the first trench region in the substrate. A lower material layer may fill the first and second trench regions. The lower material layer may be etched by a first etching process to form a first preliminary lower material layer pattern remaining in the first trench region and form a second preliminary lower material layer pattern that remains in the second trench region. An upper surface of the second preliminary lower material layer pattern may be at a different height than the first preliminary lower material layer pattern. The first and second preliminary lower material layer patterns may be etched by a second etching process to form first and second lower material layer patterns having top surfaces at substantially the same height.Type: GrantFiled: July 11, 2008Date of Patent: August 24, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Kyung-Mun Byun, Ju-Seon Goo, Sang-Ho Rha, Eun-Kyung Baek, Jong-Wan Choi
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Publication number: 20090045483Abstract: A semiconductor device may include a semiconductor substrate, trench region, buffer pattern, gap fill layer, and transistor. The trench region may be provided in the semiconductor substrate to define an active region. The buffer pattern and gap fill layer may be provided in the trench region. The buffer pattern and gap fill layer may fill the trench region. The gap fill layer may be densified by the buffer pattern. The transistor may be provided in the active region. A method of manufacturing a semiconductor device may include: forming a trench region in a semiconductor substrate; forming a buffer layer on an inner wall of the first trench region; forming a gap fill layer, filling the trench region; performing a thermal process to react the impurity with the oxygen, forming a buffer pattern; and forming a transistor in the active region.Type: ApplicationFiled: August 13, 2008Publication date: February 19, 2009Inventors: Sang-Ho Rha, Eun-Kee Hong, Kyung-Mun Byun, Jong-Wan Choi, Eun-Kyung Baek
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Publication number: 20090020847Abstract: A semiconductor device having a trench isolation region and methods of fabricating the same are provided. The method includes forming a first trench region in a substrate, and a second trench region having a larger width than the first trench region in the substrate. A lower material layer may fill the first and second trench regions. The lower material layer may be etched by a first etching process to form a first preliminary lower material layer pattern remaining in the first trench region and form a second preliminary lower material layer pattern that remains in the second trench region. An upper surface of the second preliminary lower material layer pattern may be at a different height than the first preliminary lower material layer pattern. The first and second preliminary lower material layer patterns may be etched by a second etching process to form first and second lower material layer patterns having top surfaces at substantially the same height.Type: ApplicationFiled: July 11, 2008Publication date: January 22, 2009Inventors: Kyung-Mun Byun, Ju-Seon Goo, Sang-Ho Rha, Eun-Kyung Baek, Jong-Wan Choi
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Publication number: 20070004139Abstract: In a method of manufacturing a non-volatile semiconductor device, a mask structure is formed on a substrate. A trench is formed by partially etching the substrate using the mask structure. A preliminary isolation layer pattern is formed on the substrate to fill the trench. The preliminary isolation layer has an upper face lower than that of the mask structure. A capping layer pattern is formed on the preliminary isolation layer pattern. An opening and an isolation layer pattern are formed by removing the mask structure and a portion on a sidewall of the preliminary isolation layer pattern adjacent to the mask structure. After forming a tunnel oxide layer, a floating gate is formed on the tunnel oxide layer and a sidewall of the isolation layer pattern.Type: ApplicationFiled: June 26, 2006Publication date: January 4, 2007Inventors: Hong-Gun Kim, Kyu-Tae Na, Eun-Kyung Baek, Ju-Seon Goo, Sang-Ho Rha
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Publication number: 20060089008Abstract: Methods of manufacturing silicon oxide layers for semiconductor devices are provided in which a substrate having a recess is coated with a spin-on-glass film so that the recess is filled with the spin-on-glass film. A main thermal treatment is performed on the spin-on-glass film at about 600 to about 1,000° C. at about 1 ATM to about 50 ATM so that the spin-on-glass film is converted into a relatively dense silicon oxide layer.Type: ApplicationFiled: October 26, 2005Publication date: April 27, 2006Inventors: Eunkee Hong, Ju-Seon Goo, Kyu-Tae Na, Sang-Ho Rha