Abstract: Power semiconductor devices are provided. In one example, a power semiconductor device includes a semiconductor structure. The power semiconductor device further includes a polysilicon gate layer on the semiconductor structure in an inactive region of the semiconductor device. The power semiconductor device further includes a gate insulating pattern between the polysilicon gate layer and the semiconductor structure, the gate insulating pattern having a thickness such that a distance between the semiconductor in the inactive region and the polysilicon gate layer through the gate insulating pattern is less than about 100 nm. The power semiconductor device further includes a shunt contact structure on semiconductor structure in the inactive region. A gate insulating electric field across the gate insulating pattern associated with a displacement current is less than about 8 MV/cm.

Abstract: A semiconductor device includes a semiconductor epitaxial structure having an off-axis orientation such that a crystallographic direction of the semiconductor epitaxial structure is non-perpendicular to a planar surface of the semiconductor epitaxial structure, and a doped region in the semiconductor epitaxial structure, wherein the doped region is formed by ion implantation into the semiconductor epitaxial structure along the crystallographic direction. The doped region includes a first region and a second region, wherein the first region is perpendicular to the second region. The first region and the second region have equal widths.

Abstract: A power semiconductor device includes a semiconductor layer structure and a protective overcoating on a bonding surface of the semiconductor layer structure. The bonding surface includes a plurality of adhesion features along an interface with the protective overcoating. The adhesion features protrude from and/or are recessed in the bonding surface, and define an adhesion strength between the bonding surface and the protective overcoating that spatially varies along the interface. Related devices and fabrication methods are also discussed.

Abstract: A Schottky diode includes a semiconductor layer structure that is interposed between first and second contacts. The semiconductor layer structure comprises a current spreading layer having a first conductivity type, a drift region between the second contact and the current spreading layer, the drift region having the first conductivity type, and a first blocking junction having a second conductivity type that is opposite the first conductivity type, the first blocking junction extending downwardly from an upper surface of the semiconductor layer structure. The current spreading layer has a first conductivity type dopant concentration that is at least 1.5 times greater than a first conductivity type dopant concentration of the drift region and the current spreading layer vertically overlaps at least a portion of a lower half of the first blocking junction.

Abstract: A Schottky diode according to some embodiments includes a silicon carbide drift layer having a first conductivity type, and a junction shielding region in the drift layer. The junction shielding region has a second conductivity type opposite the first conductivity type. The Schottky diode further includes an anode contact on the silicon carbide drift layer. The anode contact includes a refractory metal nitride, and forms a Schottky junction with the drift layer and an ohmic contact to the junction shielding region.

Abstract: A semiconductor device includes a semiconductor layer having a first area and an edge termination area outside the first area. The semiconductor layer has a first conductivity type, an active area in the first area, a test area in the first area adjacent the active area, a first anode contact on the semiconductor layer in the active area, a second anode contact on the semiconductor layer in the test area, and a cathode contact in electrical contact with the semiconductor layer. A related method of testing surge current capability of a semiconductor device includes applying a forward current that is smaller than a maximum forward current of the semiconductor device to a test active area that is within an area inside a main edge termination area of the semiconductor device, and detecting a failure of the semiconductor device in response to the forward current.

Abstract: A semiconductor device includes a semiconductor layer including an active area, a first implanted region within the active area at a surface of the semiconductor layer, and an integrated test area in the semiconductor layer. The integrated test area includes a second implanted region in the semiconductor layer.

Abstract: A method of forming a semiconductor device comprises forming a first mask that includes a longitudinally-extending first opening that has a first width on a semiconductor layer structure. A spacer is formed on sidewalls of the first mask that are exposed by the first opening to form a second mask, where the first and second masks comprise a mask structure that has a longitudinally-extending second opening that has a second width that is smaller than the first width. Dopants are implanted through the second opening to form an implanted region in the semiconductor layer structure. The spacer is at least partially removed from the sidewalls of the first mask to form a third opening in the mask structure. The semiconductor layer structure is then etched using the mask structure as an etch mask to form a gate trench in the semiconductor layer structure underneath the third opening.

Abstract: A semiconductor device includes a drift region, an active region in the drift region, and an edge termination region in the drift region adjacent to the active region. The edge termination region includes one or more guard rings in the drift region. The drift region has a first conductivity type and the one or more guard rings have a second conductivity type. The edge termination region may also include a passivation layer that is disposed on the one or more guard rings and on the drift region in the edge termination region. The passivation layer has a first thickness over each guard ring and a second thickness over the drift region, where the first thickness is greater than the second thickness. Alternatively, the edge termination region may also include a passivation layer that is only disposed on the one or more guard rings in the edge termination region.

Abstract: Power semiconductor devices comprise a gate pad, a plurality of gate fingers, and a first gate resistor and a first switch that are coupled between the gate pad and the gate fingers.

Abstract: Power semiconductor devices comprise a wide bandgap semiconductor layer structure, a gate pad on the wide bandgap semiconductor layer structure, a plurality of gate fingers on the wide bandgap semiconductor layer structure, and a plurality of lumped gate resistors electrically coupled between the gate pad and the gate fingers.

Abstract: Power semiconductor devices comprise a gate pad, a plurality of gate fingers, and a first gate resistor and a first switch that are coupled between the gate pad and the gate fingers.

Abstract: Semiconductor devices, and more particularly passivation structures for semiconductor devices are disclosed. A semiconductor device may include an active region, an edge termination region that is arranged along a perimeter of the active region, and a passivation structure that may form a die seal along the edge termination region. The passivation structure may include a number of passivation layers in an arrangement that improves mechanical strength and adhesion of the passivation structure along the edge termination region. An interface formed by at least one of the passivation layers may be provided with a pattern that serves to more evenly distribute forces related to thermal expansion and contraction during power cycling, thereby reducing cracking and delamination in the passivation structure. A patterned layer may be at least partially embedded in the passivation structure in an arrangement that forms the corresponding pattern in overlying portions of the passivation structure.

Abstract: A power semiconductor device includes a semiconductor layer structure and a protective overcoating on a bonding surface of the semiconductor layer structure. The bonding surface includes a plurality of adhesion features along an interface with the protective overcoating. The adhesion features protrude from and/or are recessed in the bonding surface, and define an adhesion strength between the bonding surface and the protective overcoating that spatially varies along the interface. Related devices and fabrication methods are also discussed.

Abstract: The organic light emitting display may include a plurality of pixels for generating light components with predetermined brightness components while controlling the amount of current that flows from a first power source to a second power source via organic light emitting diodes (OLED), a first power source controller for extracting data of the highest gray level among input data items of one frame and for outputting a control value having voltage information corresponding to the highest gray level data, and a first power source generator for generating a controlled voltage value corresponding to the control value and outputting the controlled voltage value to the first power source.

Abstract: An organic light emitting diode (OLED) display and a method of compensating for degradation are disclosed. One inventive aspect includes a panel assembly including a plurality of pixels. Luminance measuring units are formed along a perimeter of the panel assembly to measure luminance of light emitted from the pixels. A processing unit compares the measured luminance data so as to detect and also compensate for a degraded pixel.

Abstract: An organic light emitting display includes a display unit including pixels coupled to scan lines, first control lines, second control lines, and data lines, a control line driver configured to supply a first control signal and a second control signal to the pixels through the first control lines and the second control lines, a first power source driver for applying a first power to the pixels of the display unit, and a second power source driver for applying a second power to the pixels of the display unit. At least one of the first power or the second power is applied to the pixels of the display unit as voltage values having different levels during one frame. The first and second control signals and the first and second powers are concurrently provided to all of the pixels of the display unit.

Abstract: An organic light emitting diode (OLED) display and a method of compensating for degradation are disclosed. One inventive aspect includes a panel assembly including a plurality of pixels. Luminance measuring units are formed along a perimeter of the panel assembly to measure luminance of light emitted from the pixels. A processing unit compares the measured luminance data so as to detect and also compensate for a degraded pixel.

Abstract: An organic light-emitting display device that increases long range uniformity (LRU). The organic light-emitting display device includes an image display unit including a plurality of pixels defined by a plurality of scan lines and a plurality of data lines, a plurality of film type connection devices electrically connected to the image display unit and at least one DC-DC converter arranged on the plurality of film type connection devices to supply driving voltages to the image display unit.

Abstract: The organic light emitting display may include a plurality of pixels for generating light components with predetermined brightness components while controlling the amount of current that flows from a first power source to a second power source via organic light emitting diodes (OLED), a first power source controller for extracting data of the highest gray level among input data items of one frame and for outputting a control value having voltage information corresponding to the highest gray level data, and a first power source generator for generating a controlled voltage value corresponding to the control value and outputting the controlled voltage value to the first power source.