Abstract: Proposed are an inductor and a manufacturing method thereof. More particularly, proposed are an inductor capable of mass production by simplifying the manufacturing process while satisfying the needs for miniaturization and low resistance, and a manufacturing method thereof.

Abstract: Operating a selector device that controls access of a signal to a memory element may comprise applying a main operating voltage pulse and a refresh voltage pulse to the selector device. The refresh voltage pulse and main operating voltage pulse have opposite polarities. A magnitude of the main operating voltage pulse is greater than or equal to a threshold voltage for turning on the selector device, and a maximum magnitude of the refresh voltage pulse is less than the threshold voltage. The refresh voltage pulse reduces a difference between the threshold voltage and a turn-off voltage of the selector device, and may be applied immediately before or immediately after the main operating voltage pulse. An electronic circuit may include the selector device and a driving circuit for apply the pulses. A nonvolatile memory may include the driving circuit and a plurality of nonvolatile memory elements each including a selector device.

Abstract: An embodiment is a seat height gear system including a monopost apparatus configured to be mounted under a seat, the monopost apparatus comprising a lower post and an upper post, and a direct drive motor apparatus within the monopost apparatus, the direct drive motor apparatus including a motor and a gear unit, the gear unit including a pinion and a rack bar, the rack bar being configured to be engaged with the pinion, the motor being fixed to the lower post of the monopost apparatus, the pinion being coupled to the motor, the rack bar being fixed to an upper post of the monopost apparatus, the motor being configured to rotate the pinion, and the rack bar being configured to convert the rotation of the pinion into the linear motion.

Abstract: A user authentication method and a user authentication apparatus acquire an input image including a frontalized face of a user, calculate a confidence map including confidence values, for authenticating the user, corresponding to pixels with values maintained in a depth image of the frontalized face of the user among pixels included in the input image, extract a second feature vector from a second image generated based on the input image and the confidence map, acquire a first feature vector corresponding to an enrolled image, and perform authentication of the user based on a correlation between the first feature vector and the second feature vector.

Abstract: A processor-implemented method with object tracking includes: determining an initial template image based on an input bounding box and an input image; generating an initial feature map by extracting features from the initial template image; generating a transformed feature map by performing feature transformation adapted to objectness on the initial feature map; generating an objectness probability map and a bounding box map indicating bounding box information corresponding to each coordinate of the objectness probability map by performing objectness-based bounding box regression analysis on the transformed feature map; and determining a refined bounding box based on the objectness probability map and the bounding box map.

Abstract: An electronic device may include a semiconductor memory structured to include a plurality of memory cells, wherein each of the plurality of memory cells may comprise: a first electrode layer; a second electrode layer; and a selection element layer disposed between the first electrode layer and the second electrode layer to electrically couple or decouple an electrical connection between the first electrode layer and the second electrode layer based on a magnitude of an applied voltage or an applied current with respect to a threshold magnitude, wherein the selection element layer has a dopant concentration profile which decreases from an interface between the selection element layer and the first electrode layer toward an interface between the selection element layer and the second electrode layer.

Abstract: A processor-implemented object tracking method includes: setting a suppressed region in a template image based on a shape of a target box of the template image; refining a template feature map of the template image by suppressing an influence of feature data corresponding to the suppressed region in the template feature map; and tracking an object by determining a bounding box corresponding to the target box in a search image based on the refined template feature map.

Abstract: A selective non-volatile memory programming method for a selected memory cell in a memory array is described so as to reduce or avoid program disturbance on an unselected memory cell. This selective programming method comprises: applying a programming pulse to a selected memory cell to be programmed and an unselected memory cell, wherein the programming pulse allows a change of the unselected memory cell within a range specified; boosting a region of the unselected memory cell; and setting a threshold time of the programming pulse, wherein the threshold time is defined when an absolute magnitude of a voltage difference between a floating gate of the unselected memory cell and the boosted region of the unselected memory cell reaches a threshold value defined.

Abstract: In an embodiment, a first machine learning (ML) model is trained using a first portion of a training data set and a second ML model is trained using a second portion of the training data set. A prediction on data samples in the second portion by the first ML model is used to correct labels on noisy data samples in the second portion. A prediction on data samples in the first portion by the second ML model is used to correct labels on noisy data samples in the first portion. The first and second ML models are retrained after the labels of the noisy data samples have been replaced with corrective labels. After a number of iterations in retraining, the cross-label-correction may be performed again. After a certain number of cross-label-corrections, the training data in the first portion and the second portion is swapped to further train the models.

Abstract: Disclosed is a nonvolatile memory device including a plurality of memory cells operable to store data, each memory cell structured to include a resistance change layer exhibiting different resistance states with different resistance values for representing data, a write circuit suitable for generating a write pulse in a write mode to write data in a memory cell of the plurality of memory cells, and a read circuit suitable for generating a read pulse in a read mode to read data from a memory cell of the plurality of memory cells, wherein the memory cells are each structured to be operable in writing or reading data when a range of a voltage level change of the read pulse corresponding to a pulse width change of the read pulse is within a range of a voltage level change of the write pulse corresponding to a pulse width change of the write pulse.

Abstract: A non-volatile synapse circuit of a non-volatile neural network. The synapse includes: a first input signal line for providing a first input signal; a reference signal line for providing a reference signal; first and second output lines for carrying first and second output signals therethrough, and first and second cells for generating the first and second output signals, respectively. Each of the first and second cells includes: a first upper select transistor having a gate that is electrically coupled to the first input signal line; and a first resistive changing element having one end connected to the first select transistor in series and another end electrically coupled to the reference signal line. The value of the first resistive changing element may be programmable to change the magnitude of an output signal.

Abstract: An electronic device may include a semiconductor memory structured to include a plurality of memory cells, wherein each of the plurality of memory cells may comprise: a first electrode layer; a second electrode layer; and a selection element layer disposed between the first electrode layer and the second electrode layer to electrically couple or decouple an electrical connection between the first electrode layer and the second electrode layer based on a magnitude of an applied voltage or an applied current with respect to a threshold magnitude, wherein the selection element layer has a dopant concentration profile which decreases from an interface between the selection element layer and the first electrode layer toward an interface between the selection element layer and the second electrode layer.

Abstract: An iron-steamer appliance includes: a housing including an internal water reservoir; a sole plate attached under the housing, the sole plate including first vents; first and second steam chambers in fluid communication with the water reservoir, wherein the first steam chamber is in fluid communication with the first vents; and a steamer nozzle in fluid communication with the second steam chamber, the steamer nozzle including second vents. The steamer nozzle is movable between retracted and extended positions, wherein in the retracted position, the nozzle is located directly above a peripheral footprint defined by the sole plate, and in the extended position, the nozzle is located at least partially forwardly of the sole plate peripheral footprint, and wherein in moving from the retracted position to the extended position, the steamer nozzle moves substantially parallel to the sole plate.

Abstract: A driver circuit for operating a memory cell, adapted to be coupled to at least one memory cell through a respective output node, said driver circuit including: a first circuit for supplying the memory cell with a first read reference voltage through the output node; a second circuit for supplying the memory cell with a second read reference voltage through the output node; and a third circuit for controlling an operation of the second circuit, wherein a range of the second read reference voltage at the output node at the output node is wider than a range of the first read reference voltage at the output node during a read operation on the memory cell.

Abstract: A semiconductor device may include: a first conductive line; a second conductive line disposed over the first conductive line to be spaced apart from the first conductive line; a variable resistance layer disposed over the first conductive line and below the second conductive line; at least one of a first dielectric layer or a second dielectric layer; at least one of a first contact or a second contact; and at least one of a first doped selector layer or a second doped selector layer.

Abstract: A semiconductor device may include at least one memory cell. The memory cell may include: a first electrode layer; a second electrode layer; and a self-selecting memory layer interposed between the first electrode layer and the second electrode layer and exhibits different resistance states for storing data and is structured to be either electrically conductive or electrically non-conductive in response to a voltage applied to the first and second electrode layers, wherein the self-selecting memory layer includes a ferroelectric layer exhibiting deep traps for trapping conductive carriers and a first dopant doped in the ferroelectric layer to form shallow traps providing a conductive path for conductive carriers to move in the ferroelectric layer.

Abstract: A semiconductor memory may include: a first variable resistance element including a first terminal and a second terminal; a second variable resistance element including a first terminal, a second terminal, and a third terminal; a first transistor configured to control an electrical connection between a first conductive line and the first terminal of the first variable resistance element; a second transistor configured to control an electrical connection between the first conductive line and the first terminal of the second variable resistance element; a connection layer structured to electrically connect the second terminal of the first variable resistance element to the second and third terminals of the second variable resistance element; and a third conductive line is electrically connected to the connection layer.

Abstract: A semiconductor memory may include at least one memory cell. The memory cell may include: a first electrode layer; a second electrode layer separated from the first electrode layer, wherein the first and second electrode layers are coupled to receive a voltage applied to the first and second electrode layers; and a self-selecting memory layer interposed between the first electrode layer and the second electrode layer and configured to store data and operable to disconnect or connect a conducting path between the first electrode layer and the second electrode layer, to respond to the voltage applied to the first and second electrode layers, wherein the self-selecting memory layer includes an insulating material layer, a first dopant that creates a shallow trap providing a path for conductive carriers in the insulating material layer, and a second dopant that is movable in the insulating material layer according to a polarity of the voltage applied to the first and second electrode layers.

Abstract: A semiconductor device including at least one memory cell is provided. The memory cell includes: a first electrode layer; a second electrode layer; a selection element layer coupled between the first electrode layer and the second electrode layer; and an insulating layer coupled between the first electrode layer and the second electrode such that a side surface of the insulating layer is in contact with a side surface of the selection element layer, wherein the selection element layer includes an insulating material doped with a first element, and wherein the insulating layer includes the insulating material doped with the first element at a lower concentration than the selection element layer, or the insulating material not doped with the first element.

Abstract: Provided is a meta-optics including a waveguide layer including a first surface and a second surface opposite to the first surface; and a plurality of meta units provided on the waveguide layer, each meta unit of the plurality of meta units including a grating configured to diffract incident light of a predetermined wavelength, a first electrode provided under the grating, a dielectric layer provided over the grating, and a second electrode provided on the dielectric layer, wherein a dielectric constant of the grating and a reflectance of the grating with respect to incident light change based on a voltage applied to the first electrode and the second electrode.