Abstract: The present disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device. A semiconductor device includes a gate stacked structure including insulating layers and conductive layers stacked alternately with each other, a first plug pattern and a second plug pattern extending in a vertical direction corresponding to a stacking direction of the gate stacked structure, first data storage layers disposed between the first plug pattern and the conductive layers and second data storage layers disposed between the second plug pattern and the conductive layers, an isolation structure extending in the vertical direction and separating the first plug pattern and the second plug pattern from each other, and insulating patterns disposed between the first data storage layers adjacent to each other in the vertical direction and the second data storage layers adjacent to each other in the vertical direction.

Abstract: A method of programming a three-dimensional semiconductor memory device includes applying a first word line programming voltage to a selected word line among the word lines, floating unselected word lines among the word lines, and applying a back-gate pass voltage to the back-gate electrode; applying a first word line verification voltage to the selected word line, applying a word line pass voltage to the unselected word lines, and applying a first back-gate verification voltage to the back-gate electrode; applying a second word line programming voltage to the selected word line, floating the unselected word lines, and applying the back-gate pass voltage to the back-gate electrode; and applying a second word line verification voltage to the selected word line, applying the word line pass voltage to the unselected word lines, and applying a second back-gate verification voltage to the back-gate electrode.

Abstract: A semiconductor device may include a first support including a first inclined surface, a first gate structure including first insulating layers and first conductive layers alternately stacked along the first inclined surface, a second support positioned over or on the first support and including a second inclined surface, a second gate structure including second insulating layers and second conductive layers alternately stacked along the second inclined surface, a first contact plug extending through the second gate structure and connected to at least one first conductive layer among the first conductive layers, and a second contact plug disposed over or on the second gate structure and connected to at least one second conductive layer among the second conductive layers.

Abstract: There are provided a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a lower interlayer insulating layer, an upper interlayer insulating layer, a channel pattern passing through the lower interlayer insulating layer and the upper interlayer insulating layer, a conductive layer facing the channel pattern between the lower interlayer insulating layer and the upper interlayer insulating layer, and a storage pattern arranged in a lateral groove, the lateral groove defined between the conductive layer and the channel pattern by the lower interlayer insulating layer and the upper interlayer insulating layer protruding toward the channel pattern more than the conducive layer, in which a distance from the conductive layer from the channel pattern decreases toward an end of the lateral groove.

Abstract: A semiconductor device includes: a stack structure including conductive patterns and insulating layers, which are alternately stacked; a channel structure penetrating the stack structure; and a memory layer penetrating the stack structure, the memory layer being disposed between the channel structure and the stack structure. The memory layer includes memory parts and dummy parts, which are alternately arranged. Each of the memory parts includes a first part between the insulating layers and a second part between the dummy parts. The first part of the memory parts have ferroelectricity.

Abstract: A method of manufacturing a semiconductor device includes forming a stacked structure with first material layers and second material layers that are alternately stacked with each other, forming a first opening that passes through the stacked structure, forming second openings between the first material layers, forming first sacrificial layers in the second openings, forming first isolation layers that protrude into the first opening by oxidizing the first sacrificial layers, forming mold patterns on the first material layers between the protruding portions of the first isolation layers, forming third openings by etching portions of the first isolation layers that are exposed between the mold patterns, forming second sacrificial layers in the third openings, and forming second isolation layers that protrude farther toward the center of the first opening than the mold patterns by oxidizing the second sacrificial layers.

Abstract: Provided herein may be a semiconductor device and a method of manufacturing the same. The semiconductor device may include a gate stacked structure including insulating layers and conductive layers that are alternatingly stacked, a hole extending in a vertical direction into the gate stacked structure, and including a first sidewall and a second sidewall facing each other, a first separation pattern and a second separation pattern that contact a boundary portion between the first sidewall and the second sidewall, the first and second separation patterns facing each other and extending in the vertical direction, a first plug pattern contacting the first sidewall and extending in the vertical direction, and a second plug pattern contacting the second sidewall and extending in the vertical direction.

Abstract: A semiconductor device includes: a stack structure including conductive patterns and insulating layers, which are alternately stacked; a channel structure penetrating the stack structure; and a memory layer penetrating the stack structure, the memory layer being disposed between the channel structure and the stack structure. The memory layer includes memory parts and dummy parts, which are alternately arranged. Each of the memory parts includes a first part between the insulating layers and a second part between the dummy parts. The first part of the memory parts have ferroelectricity.

Abstract: A semiconductor memory device Includes a gate stack, a first data storage segment and a second data storage segment. The gate stack includes a first and second concave portions, which face opposite directions. The first and second t data storage segments correspond to the first and second concave portions.

Abstract: A method of manufacturing a semiconductor device includes forming a stacked structure with first material layers and second material layers that are alternately stacked with each other, forming a first opening that passes through the stacked structure, forming second openings between the first material layers, forming first sacrificial layers in the second openings, forming first isolation layers that protrude into the first opening by oxidizing the first sacrificial layers, forming mold patterns on the first material layers between the protruding portions of the first isolation layers, forming third openings by etching portions of the first isolation layers that are exposed between the mold patterns, forming second sacrificial layers in the third openings, and forming second isolation layers that protrude farther toward the center of the first opening than the mold patterns by oxidizing the second sacrificial layers.

Abstract: A semiconductor device includes a stacked structure with insulating layers and conductive layers that are alternately stacked on each other, a hard mask pattern on the stacked structure, a channel structure penetrating the hard mask pattern and the stacked structure, insulating patterns interposed between the insulating layers and the channel structure, wherein the insulating patterns protrude farther towards the channel structure than a sidewall of the hard mask pattern, and a memory layer interposed between the stacked structure and the channel structure, wherein the memory layer fills a space between the insulating patterns.

Abstract: A semiconductor device includes a stacked structure with insulating layers and conductive layers that are alternately stacked on each other, a hard mask pattern on the stacked structure, a channel structure penetrating the hard mask pattern and the stacked structure, insulating patterns interposed between the insulating layers and the channel structure, wherein the insulating patterns protrude farther towards the channel structure than a sidewall of the hard mask pattern, and a memory layer interposed between the stacked structure and the channel structure, wherein the memory layer fills a space between the insulating patterns.

Abstract: A semiconductor memory device, and a method of manufacturing the same, includes a gate stack including a plurality of gate patterns and a plurality of interlayer insulating layers alternately stacked with each other in a cell region, a source line disposed on the gate stack, and a channel plug passing through the gate stack and the source line in a vertical direction. The channel plug includes a backgate, a backgate insulating layer surrounding a sidewall of the backgate, a channel layer surrounding the sidewall of the backgate, and a memory layer surrounding a sidewall of the channel layer. The backgate insulating layer extends between the backgate and the source line.

Abstract: Provided herein may be a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device may include a gate stacked structure including a plurality of insulating layers and a plurality of conductive layers that are alternately stacked, a vertical structure extending into the gate stacked structure, a floating gate disposed between the vertical structure and the plurality of conductive layers, and a dielectric pattern disposed between the floating gate and the plurality of conductive layers. The floating gate may include a first portion that is adjacent to the vertical structure and a second portion that is adjacent to the dielectric pattern, and the dielectric pattern may contact an upper surface, a lower surface, and a sidewall of the second portion.

Abstract: A three dimensional semiconductor device is disclosed. The tree dimensional semiconductor device includes a word line stack over a substrate and a channel pillar structure passing through the word line stack in a vertical direction perpendicular to a top surface of the substrate. The channel pillar structure includes a channel structure. The channel structure includes a blocking layer, a trap layer, a tunneling layer, a channel layer, a filling layer, and a back gate electrode. The channel structure has a pillar shape.

Abstract: Provided herein are a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a gate stacked body including a plurality of interlayer insulating layers and a plurality of conductive layers that are alternately stacked, wherein a top-most conductive layer, among the plurality of conductive layers, corresponds to a backgate line and the rest of the plurality of conductive layers correspond to word lines, and a vertical channel structure passing through the gate stacked body. A first part of the vertical channel structure passing through the plurality of interlayer insulating layers and the plurality of conductive layers corresponding to the word lines has a circular structure in a plan view, and a second part of the vertical channel structure passing through the conductive layer corresponding to the backgate line has a pair of semicircular structures that are separated from each other in a plan view.

Abstract: A semiconductor device includes a stack structure including conductive patterns spaced apart from each other, a channel structure penetrating the stack structure, and a slit insulating layer penetrating the stack structure. Air gaps are defined between the conductive patterns. The slit insulating layer includes a first interposition part covering a sidewall of one of the conductive patterns and a second interposition part covering one of the air gaps from the side. A smallest width of the second interposition part is smaller than a smallest width of the first interposition part.

Abstract: Provided herein may be a resistive memory device and a method of operating the resistive memory device. The resistive memory device may include strings coupled between one or more source lines and one or more bit lines, each string including a set of one or more resistive memory cells, one or more word lines respectively coupled to the set of one or more resistive memory cells; and a voltage generator configured to control a level of a turn-on voltage to be applied to one or more unselected word lines among the one or more word lines depending on a program target state of a subset of resistive memory cells including one or more resistive memory cells selected from among the set of one or more resistive memory cells.

Abstract: The present technology relates to a resistive memory device and a method of manufacturing the same. The resistive memory device includes a stack structure in which a plurality of interlayer insulating layers and a plurality of conductive layers are alternately stacked, a hole passing through the stack structure in a vertical direction, a gate insulating layer, a channel layer, and a variable resistance layer sequentially formed along a sidewall of the hole, and a high dielectric layer formed between the channel layer and the gate insulating layer, the high dielectric layer being adjacent to the plurality of interlayer insulating layers.

Abstract: A semiconductor device includes a stack structure including conductive patterns spaced apart from each other, a channel structure penetrating the stack structure, and a slit insulating layer penetrating the stack structure. Air gaps are defined between the conductive patterns. The slit insulating layer includes a first interposition part covering a sidewall of one of the conductive patterns and a second interposition part covering one of the air gaps from the side. A smallest width of the second interposition part is smaller than a smallest width of the first interposition part.