Abstract: Systems and methods are described including a page buffer to reduce a threshold voltage distribution skew of memory cells and improve programming performance. The page buffer includes a first circuit element connected to a first terminal for supplying a first bitline voltage, a second circuit element connected to a second terminal for supplying a second bitline voltage, and a latch configured to control the first and second circuit elements.

Abstract: A semiconductor device includes a stacked structure with insulating layers and conductive layers that are alternately stacked on each other, a hard mask pattern located on the stacked structure, a channel structure penetrating the hard mask pattern and the stacked structure, insulating patterns interposed between the insulating layers and the channel structure, and a memory layer interposed between the stacked structure and the channel structure, wherein the memory layer fills a space between the insulating patterns, wherein a sidewall of each of the conductive layers protrudes farther towards the channel structure than a sidewall of the hard mask pattern, and wherein the insulating patterns protrude farther towards the channel structure than the sidewall of each of the conductive layers.

Abstract: A semiconductor device includes a stacked structure with insulating layers and conductive layers that are alternately stacked on each other, a hard mask pattern on the stacked structure, a channel structure penetrating the hard mask pattern and the stacked structure, insulating patterns interposed between the insulating layers and the channel structure, wherein the insulating patterns protrude farther towards the channel structure than a sidewall of the hard mask pattern, and a memory layer interposed between the stacked structure and the channel structure, wherein the memory layer fills a space between the insulating patterns.

Abstract: A semiconductor device includes a stacked structure including insulating layers and conductive layers alternately stacked on each other, a hard mask pattern located on the stacked structure, a channel structure passing through the hard mask pattern and the stacked structure, insulating patterns interposed between the insulating layers and the channel structure and each including a first surface and a second surface, wherein the first surface faces each of the insulating layers and is flat and the second surface faces the channel structure and includes a curved surface, and a memory layer interposed between the stacked structure and the channel structure and filling a space between the insulating patterns, wherein a sidewall of each of the conductive layers is located on an extending line of a sidewall of the hard mask pattern and the insulating patterns protrude farther towards the channel structure than the sidewall of the hard mask pattern.

Abstract: The present disclosure provides an air heater. The air heater comprises: a direct heat generating portion configured to be heated by an electric current supplied from outside; an indirect heat generating portion configured to be heated by conductive heat, which is supplied by physical contact with the heated direct heat generating portion, and configured to heat air coming in through an inlet opening formed on one side while the air is passing through an outlet opening formed on the other side; and a housing made of an insulating material that provides a space where the direct heat generating portion and the indirect heat generating portion are placed, and that comprises an air inlet on one side through which the air is drawn in from outside and an air vent on the other side through which the air is released.

Abstract: A semiconductor device includes a stacked structure on a substrate. The stacked structure includes stepped regions and a central region between the stepped regions, an upper insulation layer on the stacked structure, and a capping insulation layer on the stepped regions of the stacked structure. The capping insulation layer includes a first upper end portion and a second upper end portion that are adjacent to the upper insulation layer. The upper insulation layer is between the first upper end portion and the second upper end portion. The first upper end portion and the second upper end portion extends a first height relative to the substrate that is different from a second height relative to the substrate of the second upper end portion.

Abstract: A display device includes a flexible substrate including a display area and a non-display area. The substrate has a first surface and a second surface opposite to the first surface. A first protection film is disposed on the first surface of the substrate. The first protection film is disposed over the display area of the substrate. A second protection film is disposed on the first surface of the substrate. The second protection film is disposed over the non-display area of the substrate. A light transmittance of the first protection film is higher than that of the second protection film.

Abstract: A three-dimensional (3D) semiconductor memory device includes a peripheral logic structure disposed on a first substrate, a horizontal semiconductor layer disposed on a second substrate, a plurality of stack structures on the horizontal semiconductor layer in a first direction, wherein the plurality of stack structures include a memory cell region and a capacitor region, a plurality of electrode isolation regions extending in the first direction and a second direction and configured to separate the plurality of stack structures to be connected to the horizontal semiconductor layer and a plurality of through-via structures having a first side connected to a through channel contact through at least one metal pad, wherein a capacitor is formed between each of electrode pads and at least one of electrode isolation regions in the plurality of stack structures or at least one of the plurality of through-via structures.

Abstract: A three-dimensional (3D) semiconductor memory device includes a peripheral logic structure on a substrate and including a peripheral circuits, horizontal semiconductor layers on the peripheral logic structure, a stack structures in which mold layers and electrode pads are alternately stacked in a first direction on the horizontal semiconductor layers, electrode isolation regions separating the stack structures and extending in the first direction and a second direction, the electrode isolation regions being connected to the horizontal semiconductor layers, and through-via structures in the peripheral logic structure. The through-via structures penetrate the stack structures in the first direction. Each of the through-via structures have one side connected to a corresponding one of the through channel contacts. Capacitors are formed by electrode pads respectively with at least one of the electrode isolation regions or with at least one of the through-via structures.

Abstract: The present disclosure relates to a pliable carbonaceous pocket composite structure including various particles encapsulated within pliable carbonaceous pockets formed by carbonaceous sheets, a method for preparing the pliable carbonaceous pocket composite structure which enables ultrafast mass production of the pliable carbonaceous pocket composite structure, an electrode including the pliable carbonaceous pocket composite structure, and an energy storage device including the electrode.

Abstract: A touch panel includes: a substrate having a first region and a second region. A plurality of sensing cells are disposed in the first region and a pad portion is disposed in the second region. An insulating interlayer is disposed on the plurality of sensing cells, a connection pattern is disposed on the insulating interlayer, with the connection pattern being electrically connected to adjacent sensing cells through contact holes. A transparent conductive pattern is disposed in the second region and on the insulating interlayer, with the transparent conductive pattern being electrically connected to the plurality of sensing cells and the pad portion.

Abstract: A touch sensor is disclosed to include a first mesh touch electrode formed in a first direction and transmitting a first touch signal, a first supplementary mesh touch electrode formed on the same layer as the first mesh touch electrode, an insulating layer covering the first mesh touch electrode and the first supplementary mesh touch electrode and having a contact cutout, a second mesh touch electrode formed in a second direction crossing the first direction and transmitting a second touch signal, and a second supplementary mesh touch electrode formed on the same layer as the second mesh touch electrode. In this touch sensor, the first mesh touch electrode is connected to the second supplementary mesh touch electrode through the contact cutout and the second mesh touch electrode is connected to the first supplementary mesh touch electrode through the contact cutout.

Abstract: The present disclosure relates to an oven having a guide member capable of automatically withdrawing an oven rack from the inside of a cooking chamber when a door is opened and a rail detachably coupled to the cooking chamber and the oven rack to move the oven rack in the front-rear direction. The oven includes a main body, a cooking chamber provided inside the main body and having an open front side, a door rotatably coupled to the main body to open and close the cooking chamber, an oven rack provided inside the cooking chamber to be movable in the front-rear direction and supporting a plurality of shelves, and a guide member connected to the oven rack according to opening and closing of the door to guide the oven rack to be moved in the front-rear direction, and separated from the oven rack when the door is completely opened.

Abstract: An input/output circuit includes a data buffer group configured to buffer data received through data lines, a data strobe buffer configured to buffer a data strobe signal to output a buffered data strobe clock, a digitally controlled delay line configured to output delay data by controlling skew of the buffered data according to a delay code, a data strobe clock output circuit configured to generate a delay data strobe clock in response to the buffered data strobe clock, a sampler configured to sample the delay data according to the delay data strobe clock to output sampled data, and a de-skew circuit configured to update the delay code according to the sampled data.

Abstract: Systems and methods are described including a page buffer to reduce a threshold voltage distribution skew of memory cells and improve programming performance. The page buffer includes a first circuit element connected to a first terminal for supplying a first bitline voltage, a second circuit element connected to a second terminal for supplying a second bitline voltage, and a latch configured to control the first and second circuit elements.

Abstract: The present disclosure relates to a pseudocapacitive conductive composite including conductive polymer chains formed on a graphene sheet, a composite for an electrode including sub-nanoscale particles of a metal oxide or metal sulfide formed on a graphene sheet, and an aqueous hybrid capacitor including the composites as electrode active materials.

Abstract: A filter assembly includes a filter holder into which a part of the filter is insertable, and a lock mounted to the filter holder and configured to lock and release the filter to and from the filter holder. The lock includes a guide coupled to the filter holder and configured to be linearly movable to transmit a force in a direction into which the filter is inserted, a pusher configured to transmit a force in a direction opposite to the direction, into which the filter is inserted, by an elastic member, a stopper rotatably received in the pusher to be arranged between the pusher and the guide, and configured to linearly move the filter holder by being linearly moved by the guide and the pusher, and a cam configured to lock and release the filter to and from the filter holder by guiding rotation and linear movement of the stopper.

Abstract: The present invention relates to a display film and, more particularly, to a display film comprising a substrate layer and a coating layer formed on one surface of the substrate layer, wherein a first critical radius of curvature measured in a direction in which the side surface of the coating layer becomes concave is at most about 10 mm, and a second critical radius of curvature measured in a direction in which the side surface of the substrate layer becomes concave is at most about 5 mm. The display film according to the present invention has a high surface hardness while exhibiting superior flexibility in both directions vertical to the plane direction of the film and thus is suitable for application as an outer window film for a display and particularly has the property of being applicable to a flexible display.

Abstract: The present disclosure relates to a particle including at least one atomic-scale channel formed on a surface of the particle or on a surface and inside of the particle; a catalyst including the particle, particularly a catalyst for efficient and selective electrochemical conversion of carbon dioxide into high value-added C2+ fuel; and a method of preparing the particle.

Abstract: A display device is provided. The display device includes an anti-reflection film. The anti-reflection film includes a base film, a retardation coating layer disposed on a first side of the base film so as to delay a phase of transmitted light, and a polarizer coating layer disposed on a second side of the base film so as to allow a polarization component of the transmitted light in a specific direction to pass through, wherein the retardation coating layer and the polarizer coating layer are formed by applying a liquid crystal on the base film.