Abstract: The present invention relates to a method for measuring channel quality information in a system transmitting a signal via a plurality of component carriers. The method comprises the steps of: measuring a channel quality value of at least one component carrier allocated to a terminal from among a plurality of component carriers used to transmit a signal from a serving cell, to which the terminal belongs, to the terminal; comparing the channel quality value with a critical value for determining whether or not a channel quality of a component carrier not allocated to the terminal from among the plurality of component carriers must be derived; and, if the channel quality value is less than the critical value, measuring a channel quality value of a component not allocated to the terminal from among the plurality of component carriers.

Abstract: Provided are a nonvolatile memory and related method of programming same. The nonvolatile memory includes a memory cell array with a plurality of nonvolatile memory cells and a write circuit. The write circuit is configured to write first logic state data to a first group of memory cells during a first program operation using an internally generated step-up voltage, and second logic state data to a second group of memory cells during a second program operation using an externally supplied step-up voltage.

Abstract: A method of transmitting and receiving channel bandwidth information in a wireless communication system is disclosed, by which backward compatibility can be maintained. The present invention includes transmitting the channel bandwidth information including information on a maximum number of resource blocks available for a mobile station supporting the first system and transmitting information on a number of resource blocks available for a mobile station supporting the second system.

Abstract: A method of configuring a radio connection in a multiple cell system is provided. The method includes configuring a first radio connection between a user equipment (UE) and a primary base station (BS) and a second radio connection between the UE and a secondary BS based on a cooperative transmission configuration in which a plurality of BSs transmit the same data to the UE, receiving first channel state regarding the first radio connection and second channel state regarding the second radio connection from the UE, releasing at least one radio connection of the first radio connection and the second radio connection, the at least one radio connection having a worse channel state than a threshold, transmitting to the UE, a new cooperative transmission configuration changed by the release of the at least one radio connection, and receiving a layer reconfiguration complete message indicating completion of layer reconfiguration based on the new cooperative transmission configuration.

Abstract: Disclosed is a method of producing an automobile interior material or construction sheet with excellent processability, and its product made therefrom. More particularly, a method comprises by carding short fibers wherein short fibers are mixed with polypropylene fibers and polyethylene fibers in a mixing ratio of 3 to 7:7 to 3, on one side or both sides of a foamed layer produced by foaming any one selected from the group consisting of polypropylene chips, polyethylene chips, polyurethane chips, and expanded polystyrene chips; setting the short fibers with a shape of a truss in the foamed layer by interlacing the short fibers through a needle punching process; and thermally forming the short fiber layer(s) on the foamed layer by heating the portions of the short fibers exposed on the outside the foamed layer to 120 to 250° C. and pressing thereby melting, cooling and hardening the fused portions of the short fibers.

Abstract: A nonvolatile memory device comprises overwritable memory cells. In an overwrite operation, data is read from a selected region of the nonvolatile memory device and combined with overwrite data to produce combined data. An error correction code is then generated for the combined data and the overwrite data and the error correction code are stored in the selected region.

Abstract: Provided are a nonvolatile memory and related method of programming same. The nonvolatile memory includes a memory cell array with a plurality of nonvolatile memory cells and a write circuit. The write circuit is configured to write first logic state data to a first group of memory cells during a first program operation using an internally generated step-up voltage, and second logic state data to a second group of memory cells during a second program operation using an externally supplied step-up voltage.

Abstract: A semiconductor device comprises a first non-volatile memory configured to store program code and a processor configured to copy the program code from the first non-volatile memory to a second non-volatile memory after a solder reflow process. The processor typically copies the program code from the first non-volatile memory to the second non-volatile memory after the processor is completely booted.

Abstract: Provided are a nonvolatile memory and related method of programming same. The nonvolatile memory includes a memory cell array with a plurality of nonvolatile memory cells and a write circuit. The write circuit is configured to write first logic state data to a first group of memory cells during a first program operation using a first internally generated step-up voltage, and second logic state data to a second group of memory cells during a second program operation using an externally supplied step-up voltage.

Abstract: A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory cells, and a control unit controlling an erase operation so that erase data is simultaneously written in the plurality of memory cells corresponding to an erase unit. A first erase mode may include a first erase unit and a first erase data pattern. A second erase mode may include a second erase unit and a second erase pattern. At least one of the first and second erase units and the first and second erase data patterns are different.

Abstract: A memory system includes a memory cell array having a plurality of memory sectors. Each memory sector includes a plurality of memory cells. The memory system further includes a controller configured to write data to the memory cell array in response to a writing signal. The controller is further configured to refresh a memory sector among the plurality of memory sectors each time a writing signal is provided. When N (N is a positive integer) memory cells are programmed, a programming current is less than or equal to about 0.75 mA*N.

Abstract: Example embodiments relate to a semiconductor memory system which may include a volatile memory and a non-volatile memory that share a common bus, and a method for controlling the operation of the non-volatile memory. The semiconductor memory system may include a non-volatile memory and a memory controller. The non-volatile memory may include a buffer memory that temporarily stores data to be read from or to be written to a memory cell array, and an internal controller. The memory controller may transmits a mode signal to the non-volatile memory in response to a control signal, the control signal corresponds to either a read mode or a write mode to be applied to the non-volatile memory. In response to the mode signal, the internal controller may control the data to be read to be stored in the buffer memory, if the read mode is to be applied, and the internal controller may control the buffer memory to stand-by until a write command is received, if the write mode is to be applied.

Abstract: Provided are a nonvolatile memory and related method of programming same. The nonvolatile memory includes a memory cell array with a plurality of nonvolatile memory cells and a write circuit. The write circuit is configured to write first logic state data to a first group of memory cells during a first program operation using a first internally generated step-up voltage, and second logic state data to a second group of memory cells during a second program operation using an externally supplied step-up voltage.

Abstract: Disclosed is a method of producing an automobile interior material or construction sheet with excellent processability, and its product made therefrom. More particularly, a method comprises by carding short fibers wherein short fibers are mixed with polypropylene fibers and polyethylene fibers in a mixing ratio of 3 to 7:7 to 3, on one side or both sides of a foamed layer produced by foaming any one selected from the group consisting of polypropylene chips, polyethylene chips, polyurethane chips, and expanded polystyrene chips; setting the short fibers with a shape of a truss in the foamed layer by interlacing the short fibers through a needle punching process; and thermally forming the short fiber layer(s) on the foamed layer by heating the portions of the short fibers exposed on the outside the foamed layer to 120 to 250° C. and pressing thereby melting, cooling and hardening the fused portions of the short fibers.

Abstract: Example embodiments relate to a semiconductor memory system which may include a volatile memory and a non-volatile memory that share a common bus, and a method for controlling the operation of the non-volatile memory. The semiconductor memory system may include a non-volatile memory and a memory controller. The non-volatile memory may include a buffer memory that temporarily stores data to be read from or to be written to a memory cell array, and an internal controller. The memory controller may transmits a mode signal to the non-volatile memory in response to a control signal, the control signal corresponds to either a read mode or a write mode to be applied to the non-volatile memory. In response to the mode signal, the internal controller may control the data to be read to be stored in the buffer memory, if the read mode is to be applied, and the internal controller may control the buffer memory to stand-by until a write command is received, if the write mode is to be applied.

Abstract: Disclosed is a pumping voltage generating circuit in a nonvolatile semiconductor memory device. The present pumping voltage generating circuit begins a pumping operation for a wordline voltage in response to an accelerating start signal activated from a supply of an external program voltage, rather than a pumping enable signal activated from a program command. According to the pumping voltage generating circuit, the wordline voltage reaches a target voltage earlier, remarkably enhancing an overall operation speed in a nonvolatile semiconductor memory device.

Abstract: A circuit and method for generating a wordline voltage in a nonvolatile semiconductor memory device. The circuit comprises a switching unit to provide an external program voltage as the wordline voltage, together with a wordline voltage pump to generate the wordline voltage by pumping a power source voltage. After the wordline voltage is raised to a first level by the external program voltage, it is further increased by a pumping operation. According the circuit and method described herein, shortens the time required to reach a target voltage.

Abstract: A circuit and method for generating a wordline voltage in a nonvolatile semiconductor memory device. The circuit comprises a switching unit to provide an external program voltage as the wordline voltage, together with a wordline voltage pump to generate the wordline voltage by pumping a power source voltage. After the wordline voltage is raised to a first level by the external program voltage, it is further increased by a pumping operation. According the circuit and method described herein, shortens the time required to reach a target voltage.

Abstract: Disclosed is a pumping voltage generating circuit in a nonvolatile semiconductor memory device. The present pumping voltage generating circuit begins a pumping operation for a wordline voltage in response to an accelerating start signal activated from a supply of an external program voltage, rather than a pumping enable signal activated from a program command. According to the pumping voltage generating circuit, the wordline voltage reaches a target voltage earlier, remarkably enhancing an overall operation speed in a nonvolatile semiconductor memory device.

Abstract: The present invention relates to an aqueous alkaline solution for mineral supplementation comprising bovine bones, cuttlefish bones, red algae and an organic acid. Also, the invention relates to a method for preparing the aqueous alkaline solution, and a composition or health food containing the aqueous alkaline solution, which is effective in the prevention and improvement in osteoporosis. The aqueous alkaline solution contains various minerals necessary for the human body at large amounts, and thus, can be used as a mineral supplement. Also, the composition prevents bone absorption and bone mineral absorption, and thus, is useful for the prevention and improvement of bone diseases, such as osteoporosis and degenerative bone diseases.