Patents by Inventor In-Seob BAE

In-Seob BAE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11966768
    Abstract: Disclosed herein are an apparatus and method for a multi-cloud service platform. The apparatus includes one or more processors and executable memory for storing at least one program executed by the one or more processors. The at least one program may receive a service request from a user client device, generate a multi-cloud infrastructure service using multiple clouds in response to the service request, make the multiple clouds interoperate with mufti-cloud infrastructure in order to provide the multi-cloud infrastructure service, and generate a multi-cloud application runtime environment corresponding to the multi-cloud infrastructure service.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: April 23, 2024
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Seok-Ho Son, Dong-Jae Kang, Byoung-Seob Kim, Seung-Jo Bae, Ji-Hoon Seo, Byeong-Thaek Oh, Kure-Chel Lee, Young-Woo Jung
  • Patent number: 11940368
    Abstract: Disclosed is a method for pre-detecting a defective porous polymer substrate for a separator, including selecting a porous polymer substrate having a plurality of pores; observing the selected porous polymer substrate with a scanning electron microscope (SEM) to obtain an image of the porous polymer substrate; quantifying the average value of pore distribution index (PDI); correcting the quantified average value of pore distribution index to obtain the corrected average value of pore distribution index; determining whether or not the corrected average value of pore distribution index is 60 a.u. (arbitrary unit) or less; and classifying the porous polymer substrate as a good product, when the corrected average value of pore distribution index is determined to be 60 a.u. or less, and classifying the porous polymer substrate as a defective product, when the corrected average value of pore distribution index is determined to be larger than 60 a.u.
    Type: Grant
    Filed: April 6, 2022
    Date of Patent: March 26, 2024
    Assignee: LG ENERGY SOLUTION, LTD.
    Inventors: Won-Sik Bae, Joo-Sung Lee, Ho-Sung Kang, Yern-Seung Kim, Se-Jung Park, Je-Seob Park, Ji-Young Hwang
  • Publication number: 20240081099
    Abstract: An organic light emitting diode display according to an exemplary embodiment includes: a substrate; a first buffer layer on the substrate; a first semiconductor layer on the first buffer layer; a first gate insulating layer on the first semiconductor layer; a first gate electrode and a blocking layer on the first gate insulating layer; a second buffer layer on the first gate electrode; a second semiconductor layer on the second buffer layer; a second gate insulating layer on the second semiconductor layer; and a second gate electrode on the second gate insulating layer.
    Type: Application
    Filed: November 9, 2023
    Publication date: March 7, 2024
    Applicant: Samsung Display Co., Ltd.
    Inventors: Joon Woo BAE, So Young KOO, Han Bit KIM, Thanh Tien NGUYEN, Kyoung Won LEE, Yong Su LEE, Jae Seob LEE, Gyoo Chul JO
  • Publication number: 20240038652
    Abstract: According to an aspect of the present disclosure, there is provided a pre-mold substrate including an electroconductive base member, which includes a first pre-mold groove formed in a bottom surface and a second pre-mold groove formed in a top surface and constitutes a circuit pattern; a first pre-mold resin disposed in the first pre-mold groove; and a second pre-mold resin disposed in the second pre-mold groove.
    Type: Application
    Filed: June 24, 2021
    Publication date: February 1, 2024
    Inventors: Kwang Jae YOO, Jong Hoe KU, In Seob BAE
  • Patent number: 11876012
    Abstract: A method of manufacturing a semiconductor package substrate includes forming a trench and a post by etching an upper surface of a base substrate including a conductive material, filling the trench with a resin, removing the resin exposed to outside of the trench such that an upper surface of the post and an upper surface of the resin are at same level, forming a conductive layer on an entire area of the upper surface of the post and the upper surface of the resin, and forming a circuit wiring including an upper circuit wiring and a lower circuit wiring by simultaneously patterning the conductive layer and a lower surface of the base substrate.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: January 16, 2024
    Assignee: HAESUNG DS CO., LTD.
    Inventors: Sung Il Kang, In Seob Bae, Jea Won Kim
  • Patent number: 11854830
    Abstract: A method of manufacturing a circuit board includes preparing a substrate having electrical conductivity, removing a portion of a first surface of the substrate to form a plurality of pillars on the first surface of the substrate, locating an insulating material on the first surface of the substrate to cover a space between the plurality of pillars of the substrate, forming a pattern on a second surface, which is opposite to the first surface of the substrate, by removing a portion of the second surface of the substrate, forming a first metal layer on the first surface of the substrate, and forming a second metal layer on the second surface of the substrate.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: December 26, 2023
    Assignee: HAESUNG DS CO., LTD.
    Inventors: Dong Jin Yoon, Sung Il Kang, In Seob Bae
  • Publication number: 20230102887
    Abstract: A lead frame includes: leads; and a dambar arranged between the leads and connecting the leads to each other, wherein each of the leads includes: a lower lead groove formed in a first surface for a wettable flank structure; and an upper lead groove formed in a second surface opposite the first surface and aligned with the lower lead groove in a thickness direction, wherein in a sawing process, a portion of the lead between the lower lead groove and the upper lead groove is at least partially removed.
    Type: Application
    Filed: September 8, 2022
    Publication date: March 30, 2023
    Inventors: Dong Jin Yoon, Sung Il Kang, In Seob BAE, Seok Kyu SEO, Dong Young Pyeon
  • Publication number: 20230080101
    Abstract: Provided are a semiconductor package substrate, a method of manufacturing the semiconductor package substrate, and a semiconductor package. According to one embodiment of the present disclosure, a semiconductor package substrate includes a base substrate having a lower surface in which a first trench is provided and an upper surface in which a second trench and a third trench are provided, including a circuit pattern and a conductive material; a first resin arranged in the first trench; and a second resin arranged in the second trench and the third trench, wherein the second trench exposes at least a part of the first resin.
    Type: Application
    Filed: September 7, 2022
    Publication date: March 16, 2023
    Inventors: Dong Jin YOON, Sung Il KANG, In Seob BAE, Seok Kyu SEO, Dong Young PYEON
  • Publication number: 20220285251
    Abstract: A semiconductor package substrate and a method of manufacturing the same are provided. The semiconductor package substrate includes: a base layer including a conductive material, having a first surface and a second surface opposite the first surface, and having a first groove or first trench in the first surface and a second groove or second trench in the second surface; a first resin buried in the first groove or first trench in the first surface of the base layer; and a groove in at least one corner of the first surface of the base layer and having a depth based on the first surface is 1/2 or more of a thickness of the base layer.
    Type: Application
    Filed: March 7, 2022
    Publication date: September 8, 2022
    Inventors: Wonbin Kim, Sung Il Kang, In Seob Bae, Dong Jin Yoon
  • Publication number: 20220274223
    Abstract: A substrate surface grinding apparatus includes: a grinding device including a plurality of grinding rollers configured to grind a surface of a substrate; and a substrate support member configured to support the substrate, wherein rotational axes of the grinding rollers are disposed to be inclined to rotational axes of adjacent grinding rollers.
    Type: Application
    Filed: February 25, 2022
    Publication date: September 1, 2022
    Inventors: Jong Hoe Ku, Sung Il Kang, I Gyun Kim, Hong Chan Kim, In Seob Bae, Jung Ho Heo
  • Patent number: 11227775
    Abstract: According to an embodiment of the disclosure, a method of fabricating a carrier for a wafer level package (WLP) by using a lead frame, wherein the lead frame is fabricated by forming a trench and a post by performing first half etching on an upper surface of a base substrate comprising a conductive material, filling the first-half-etched surface with resin of an insulating material, removing the resin exposed to outside of the trench so that an upper surface of the trench and an upper surface of the resin are at a same level, and performing second half etching on a lower surface of the base substrate, in which a memory chip is attached to the lower surface of the base substrate.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: January 18, 2022
    Assignee: HAESUNGDS CO., LTD.
    Inventors: Dong Young Pyeon, Sung Il Kang, Jong Hoe Ku, In Seob Bae
  • Publication number: 20210217629
    Abstract: A method of manufacturing a circuit board includes preparing a substrate having electrical conductivity, removing a portion of a first surface of the substrate to form a plurality of pillars on the first surface of the substrate, locating an insulating material on the first surface of the substrate to cover a space between the plurality of pillars of the substrate, forming a pattern on a second surface, which is opposite to the first surface of the substrate, by removing a portion of the second surface of the substrate, forming a first metal layer on the first surface of the substrate, and forming a second metal layer on the second surface of the substrate.
    Type: Application
    Filed: September 14, 2020
    Publication date: July 15, 2021
    Inventors: Dong Jin YOON, Sung Il KANG, In Seob BAE
  • Publication number: 20210107094
    Abstract: According to one or more embodiments, there is provided an apparatus for polishing a surface of a substrate to remove a resin layer formed on the surface of the substrate having a groove, the apparatus including: a laser irradiation apparatus configured to irradiate a laser to the resin layer to remove at least a portion of a resin from the resin layer except for a portion of the resin layer arranged in the groove.
    Type: Application
    Filed: April 13, 2020
    Publication date: April 15, 2021
    Inventors: Sung Il KANG, Se Chuel PARK, Jong Hoe KU, In Seob BAE
  • Publication number: 20210098268
    Abstract: According to an embodiment of the disclosure, a method of fabricating a carrier for a wafer level package (WLP) by using a lead frame, wherein the lead frame is fabricated by forming a trench and a post by performing first half etching on an upper surface of a base substrate comprising a conductive material, filling the first-half-etched surface with resin of an insulating material, removing the resin exposed to outside of the trench so that an upper surface of the trench and an upper surface of the resin are at a same level, and performing second half etching on a lower surface of the base substrate, in which a memory chip is attached to the lower surface of the base substrate.
    Type: Application
    Filed: April 21, 2020
    Publication date: April 1, 2021
    Inventors: Dong Young PYEON, Sung Il KANG, Jong Hoe KU, In Seob BAE
  • Patent number: 10910299
    Abstract: Provided are a method of manufacturing a semiconductor package substrate, a semiconductor package substrate manufactured using the method of manufacturing a semiconductor package substrate, a method of manufacturing a semiconductor package, and a semiconductor package manufactured using the method of manufacturing a semiconductor package. The method of manufacturing a semiconductor package substrate includes forming first grooves or first trenches in a bottom surface of a base substrate having a top surface and the bottom surface and formed of a conductive material; filling the first grooves or trenches with resin; curing the resin; removing exposed portions of the resin overfilled in the first grooves or trenches; etching the top surface of the base substrate to expose at least portions of the resin filled in the first grooves or trenches; and forming a second groove or a second trench in the bottom surface of the base substrate.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: February 2, 2021
    Assignee: HAESUNG DS CO., LTD.
    Inventors: In Seob Bae, Sung Il Kang, Dong Jin Yoon
  • Publication number: 20200411362
    Abstract: A method of manufacturing a semiconductor package substrate includes forming a trench and a post by etching an upper surface of a base substrate including a conductive material, filling the trench with a resin, removing the resin exposed to outside of the trench such that an upper surface of the post and an upper surface of the resin are at same level, forming a conductive layer on an entire area of the upper surface of the post and the upper surface of the resin, and forming a circuit wiring including an upper circuit wiring and a lower circuit wiring by simultaneously patterning the conductive layer and a lower surface of the base substrate.
    Type: Application
    Filed: September 11, 2020
    Publication date: December 31, 2020
    Inventors: Sung Il KANG, In Seob BAE, Jea Won KIM
  • Patent number: 10840170
    Abstract: A semiconductor package substrate, in which a base substrate having an upper surface and a lower surface and formed of a conductive material is filled with resin formed of an insulating material, includes a die pad formed of the conductive material on the upper surface and a lead arranged on the upper surface by being electrically separated from the die pad and comprising a bonding pad that is a wire bonding area. A protrusion protruding toward the lower surface is formed in a central area of the bonding pad. A central thickness of the bonding pad is greater than a peripheral thickness of the bonding pad.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: November 17, 2020
    Assignee: HAESUNG DS CO., LTD.
    Inventors: In Seob Bae, Sung Il Kang
  • Patent number: 10840161
    Abstract: A method of manufacturing a semiconductor package substrate includes forming a trench in one surface of a base substrate formed of a conductive material, performing a first filling operation of filling the trench with resin, performing a first curing operation of semi-curing the resin filled in the first filling operation, performing a second filling operation of additionally filling resin on a semi-cured resin, performing a second curing operation of fully curing the resin, removing the resin exposed from the trench, and etching an opposite surface of the base substrate to expose at least part of the resin filling the trench.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: November 17, 2020
    Assignee: HAESUNG DS CO., LTD.
    Inventors: In Seob Bae, Hyeok Jin Jeon
  • Patent number: 10811302
    Abstract: A method of manufacturing a semiconductor package substrate includes forming a trench and a post by etching an upper surface of a base substrate including a conductive material, filling the trench with a resin, removing the resin exposed to outside of the trench such that an upper surface of the post and an upper surface of the resin are at same level, forming a conductive layer on an entire area of the upper surface of the post and the upper surface of the resin, and forming a circuit wiring including an upper circuit wiring and a lower circuit wiring by simultaneously patterning the conductive layer and a lower surface of the base substrate.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: October 20, 2020
    Assignee: HAESUNG DS CO., LTD.
    Inventors: Sung II Kang, In Seob Bae, Jea Won Kim
  • Publication number: 20200227344
    Abstract: A semiconductor package substrate, in which a base substrate having an upper surface and a lower surface and formed of a conductive material is filled with resin formed of an insulating material, includes a die pad formed of the conductive material on the upper surface and a lead arranged on the upper surface by being electrically separated from the die pad and comprising a bonding pad that is a wire bonding area. A protrusion protruding toward the lower surface is formed in a central area of the bonding pad. A central thickness of the bonding pad is greater than a peripheral thickness of the bonding pad.
    Type: Application
    Filed: March 25, 2020
    Publication date: July 16, 2020
    Inventors: In Seob BAE, Sung Il KANG